Quotables
"To place a man in a multi-stage rocket and project him into the controlling gravitational field of the moon where the passengers can make scientific observations, perhaps land alive, and then return to earth--all that constitutes a wild dream worthy of Jules Verne. I am bold enough to say that such a man-made voyage will never occur regardless of all future advances."
Lee deForest, American radio pioneer ; 1957
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| Application No. | Application Title | Issue Date |
| 20120037957 | SEMICONDUCTOR DEVICES GROWN ON INDIUM-CONTAINING SUBSTRATES UTILIZING INDIUM DEPLETION MECHANISMS We have observed anomalous behavior of II-VI semiconductor devices grown on certain semiconductor substrates, and have determined that the anomalous behavior is likely the result of indium atoms from the substrate migrating into the II-V layers during growth. The indium... | 02/16/2012 |
| 20120018779 | METHOD FOR PRODUCING MICROMECHANICAL PATTERNS HAVING A RELIEF-LIKE SIDEWALL OUTLINE SHAPE OR AN ADJUSTABLE ANGLE OF INCLINATION A method for producing micromechanical patterns having a relief-like sidewall outline shape or an angle of inclination that is able to be set, the micromechanical patterns being etched out of a SiGe mixed semiconductor layer that is present on or deposited on a silicon ... | 01/26/2012 |
| 20120007144 | Compound Semiconductor Device and Method of Producing the Same A semiconductor device comprises an Si substrate 10 and a compound layer 11 of Si1-XGeX disposed on the substrate 10. X is varied from 0 to 0.2 away from the substrate 10 towards the upper surface of the compound layer 11, with the rate of ch... | 01/12/2012 |
| 20110235665 | COMPOSITIONALLY GRADED HETEROJUNCTION SEMICONDUCTOR DEVICE AND METHOD OF MAKING SAME A compositionally graded semiconductor device and a method of making same are disclosed that provides an efficient p-type doping for wide bandgap semiconductors by exploiting electronic polarization within the crystalline lattice. The compositional graded semiconductor ... | 09/29/2011 |
| 20110079821 | Integrated Devices on a Common Compound Semiconductor III-V Wafer A method of fabricating an integrated circuit on a compound semiconductor III-V wafer including at least two different types of active devices by providing a substrate; growing a first epitaxial structure on the substrate; growing a second epitaxial structure on the fir... | 04/07/2011 |
| 20110018031 | TRANSISTOR GATE ELECTRODE HAVING CONDUCTOR MATERIAL LAYER Various embodiments of the invention relate to a PMOS device having a transistor channel of silicon germanium material on a substrate, a gate dielectric having a dielectric constant greater than that of silicon dioxide on the channel, a gate electrode conductor material... | 01/27/2011 |
| 20100200894 | HETERO JUNCTION BIPOLAR TRANSISTOR An energy level Ec in a vicinity of an interface between a graded layer 1G a ballast resistor 1R is smoothly continuous. This is because an n-type impurity concentration CION in the vicinity of the interface is increased and thus an ionized dono... | 08/12/2010 |
| 20100066451 | Compound semiconductor device and doherty amplifier using compound semiconductor device A lower electron supply layer is disposed over a lower electron transport layer made of compound semiconductor. The lower electron supply layer is made of n-type compound semiconductor having an electron affinity smaller than that of the lower electron transport layer. ... | 03/18/2010 |
| 20090224286 | MOBILITY ENHANCEMENT IN SiGe HETEROJUNCTION BIPOLAR TRANSISTORS The present invention relates to a high performance heterojunction bipolar transistor (HBT) having a base region with a SiGe-containing layer therein. The SiGe-containing layer is not more than about 100 nm thick and has a predetermined critical germanium content. The S... | 09/10/2009 |
| 20090218589 | Semiconductor die with reduced thermal boundary resistance Thermal boundary resistances within nitride semiconductor LEDs are reduced or eliminated by forming a thick nitride epitaxial layer, which can be separated from a growth substrate, and by reducing the number of thermal boundary layers during laser lift-off. The thermal ... | 09/03/2009 |
| 20080308843 | FIELD EFFECT TRANSISTOR HAVING A COMPOSITIONALLY GRADED LAYER A GaN heterojunction FET has an AlxGa1-xN first graded layer and an AlyGa1-yN second graded layer, which are formed sequentially on a channel layer. The Al mole fraction x of the first graded layer decreases linearly from, for... | 12/18/2008 |
| 20080204140 | Compound semiconductor device and doherty amplifier using compound semiconductor device A lower electron supply layer is disposed over a lower electron transport layer made of compound semiconductor. The lower electron supply layer is made of n-type compound semiconductor having an electron affinity smaller than that of the lower electron transport layer. ... | 08/28/2008 |
| 20080173895 | Gallium nitride on silicon with a thermal expansion transition buffer layer A method is provided for forming a matching thermal expansion interface between silicon (Si) and gallium nitride (GaN) films. The method provides a (111) Si substrate with a first thermal expansion coefficient (TEC), and forms a silicon-germanium (SiGe) film overlying t... | 07/24/2008 |
| 20080142844 | SEMICONDUCTOR HETEROSTRUCTURE A semiconductor heterostructure that includes a support substrate with a first in-plane lattice parameter, a buffer structure formed on the support substrate and having on top in a relaxed state a second in-plane lattice parameter, and a multi-layer stack of ungraded la... | 06/19/2008 |
| 20080128750 | Method and system for providing a metal oxide semiconductor device having a drift enhanced channel A method and system for providing a metal oxide semiconductor (MOS) device are described. The method and system include providing a source, a drain, and a channel residing between the source and the drain. At least a portion of the channel includes an alloy layer includ... | 06/05/2008 |
| 20080128749 | Method and system for providing a drift coupled device A method and system for providing a semiconductor device is described. The method and system include providing a compound region and providing a doped region. The compound region includes an alloy having an impurity. The impurity has a graded profile in the compound reg... | 06/05/2008 |
| 20080128751 | METHODS FOR FORMING III-V SEMICONDUCTOR DEVICE STRUCTURES The benefits of strained semiconductors are combined with silicon-on-insulator approaches to substrate and device fabrication.... | 06/05/2008 |
| 20080116484 | METHOD OF ENHANCING HOLE MOBILITY A semiconductor device is provided comprising an oxide layer over a first silicon layer and a second silicon layer over the oxide layer, wherein the oxide layer is between the first silicon layer and the second silicon layer. The first silicon layer and the second silic... | 05/22/2008 |
| 20080023688 | EFFICIENT CARRIER INJECTION IN A SEMICONDUCTOR DEVICE Semiconductor devices such as VCSELs, SELs, LEDs, and HBTs are manufactured to have a wide bandgap material near a narrow bandgap material. Electron injection is improved by an intermediate structure positioned between the wide bandgap material and the narrow bandgap ma... | 01/31/2008 |
| 20080001171 | Field effect transistor, integrated circuit element, and method for manufacturing the same A field effect transistor of an embodiment of the present invention includes, a semiconductor substrate containing Si atoms; a protruding structure formed on the semiconductor substrate; a channel region formed in the protruding structure and containing Ge atoms; an und... | 01/03/2008 |
| 20070278517 | HETERO-INTEGRATED STRAINED SILICON n- AND p- MOSFETS The present invention provides semiconductor structures and a method of fabricating such structures for application of MOSFET devices. The semiconductor structures are fabricated in such a way so that the layer structure in the regions of the wafer where n-MOSFETs are f... | 12/06/2007 |
| 20070102790 | Process for deposition of semiconductor films Chemical vapor deposition processes utilize higher order silanes and germanium precursors as chemical precursors. The processes have high deposition rates yet produce more uniform films, both compositionally and in thickness, than films prepared using conventional chemi... | 05/10/2007 |
| 20070090450 | SEMICONDUCTOR DEVICE WITH HIGH DIELECTRIC CONSTANT INSULATING FILM AND MANUFACTURING METHOD FOR THE SAME A semiconductor device has a substrate and a dielectric film formed directly or indirectly on the substrate. The dielectric film contains a metal silicate film, and a silicon concentration in the metal silicate film is lower in a center portion in the film thickness dir... | 04/26/2007 |
| 20070063220 | Field-effect transistor A field-effect transistor includes a channel layer having a channel and a carrier supply layer, disposed on the channel layer, containing a semiconductor represented by the formula AlxGa1-xN, wherein x is greater than 0.04 and less than 0.45. The c... | 03/22/2007 |
| 20070018179 | VERTICAL CONDUCTING POWER SEMICONDUCTING DEVICES MADE BY DEEP REACTIVE ION ETCHING The Invention Is A Method For Making Power Device On A Semiconductor Wafer, Where The Backside Of The Wafer Has Been Thinned In Selected Regions To A Thickness Of About 25 Um By Reactive Ion Etching. ... | 01/25/2007 |
| 20060145188 | Semiconductor wafer having a silicon-germanium layer, and method for its production A semiconductor wafer has a monocrystalline silicon layer and a graded silicon-germanium layer adjacent thereto, of thickness d and composition Si1-xGex, where x represents the proportion of germanium and 0 07/06/2006 | |
| 20060054928 | Layered construction The invention relates to a layered construction for a Gunn diode. The layered construction comprises a series of stacked layers consisting of a first highly doped nd GaAs layer (3), a graded AlGaAs layer (5), which is placed upon the first highl... | 03/16/2006 |
| 20050285139 | Strained Si/SiGe structures by ion implantation One aspect of this disclosure relates to a method for forming a strained silicon over silicon germanium (Si/SiGe) structure. In various embodiments, germanium ions are implanted into a silicon substrate with a desired dose and energy to be located beneath a surface sili... | 12/29/2005 |
| 20050136584 | Strained transistor integration for CMOS Various embodiments of the invention relate to a CMOS device having (1) an NMOS channel of silicon material selectively deposited on a first area of a graded silicon germanium substrate such that the selectively deposited silicon material experiences a tensile strain ca... | 06/23/2005 |
| 20050082567 | Structure of a relaxed Si/Ge epitaxial layer and fabricating method thereof A structure of the relaxed SiGe epitaxial layer and a fabrication method comprises a Si substrate, a Si interfacial layer positioning on the substrate, a SiGe graded buffer layer positioning on the Si interfacial layer, and a uniform SiGe epitaxy layer positioning on th... | 04/21/2005 |
| 20050023554 | Si/SiGe optoelectronic integrated circuits An integrated optoelectronic circuit and process for making is described incorporating a photodetector and a MODFET on a chip. The chip contains a single-crystal semiconductor substrate, a buffer layer of SiGe graded in composition, a relaxed SiGe layer, a quantum well ... | 02/03/2005 |
