Did You Know...
...that power steering was invented by independent inventor Francis W. Davis? As chief engineer in the 1920s of the truck division of the Pierce Arrow Motor Car Company, he saw how hard it was to steer heavy vehicles. So that he would be able to keep the profits from his future invention, Davis left his job, rented a small engineering shop in Waltham, Mass., and developed a hydraulic power steering system that led to power steering.
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| Application No. | Application Title | Issue Date |
| 20110227042 | METHOD FOR PRODUCING SEMICONDUCTOR SUBSTRATE, SEMICONDUCTOR SUBSTRATE, METHOD FOR MANUFACTURING ELECTRONIC DEVICE, AND REACTION APPARATUS There is provided a method of producing a semiconductor wafer by thermally processing a base water having a portion to be thermally processed that is to be thermally processed. The method comprises a step of providing, on the base wafer, a portion to be heated that gene... | 09/22/2011 |
| 20110186816 | SEMICONDUCTOR DEVICE WAFER, SEMICONDUCTOR DEVICE, DESIGN SYSTEM, MANUFACTURING METHOD AND DESIGN METHOD A device forming thin film for forming a semiconductor device; an inhibition portion that surrounds the device forming thin film and inhibits growth of a precursor of the device forming thin film into a crystal; a sacrificial growth portion that is formed by causing the... | 08/04/2011 |
| 20110108801 | SINGLE-CRYSTAL SEMICONDUCTOR LAYER WITH HETEROATOMIC MACRO-NETWORK A single-crystal layer of a first semiconductor material including single-crystal nanostructures of a second semiconductor material, the nanostructures being distributed in a regular crystallographic network with a centered tetragonal prism.... | 05/12/2011 |
| 20110100411 | SEMICONDUCTOR NANOWIRE THERMOELECTRIC MATERIALS AND DEVICES, AND PROCESSES FOR PRODUCING SAME The present invention provides nanowires and nanoribbons that are well suited for use in thermoelectric applications. The nanowires and nanoribbons are characterized by a periodic compositional longitudinal modulation. The nanowires are constructed using lithographic te... | 05/05/2011 |
| 20100163842 | Multiple-Gate Transistors with Reverse T-Shaped Fins A method of forming an integrated circuit structure includes forming a first insulation region and a second insulation region in a semiconductor substrate and facing each other; and forming an epitaxial semiconductor region having a reversed T-shape. The epitaxial semic... | 07/01/2010 |
| 20100117059 | LIGHT MODULATION COMPRISING SI-GE QUANTUM WELL LAYERS Optical modulators include active quantum well structures coherent with pseudosubstrates comprising relaxed buffer layers on a silicon substrate. In a preferred method the active structures, consisting of Si1−x Gex barrier and well layers with di... | 05/13/2010 |
| 20090315076 | TRANSISTOR GATE ELECTRODE HAVING CONDUCTOR MATERIAL LAYER Various embodiments of the invention relate to a PMOS device having a transistor channel of silicon germanium material on a substrate, a gate dielectric having a dielectric constant greater than that of silicon dioxide on the channel, a gate electrode conductor material... | 12/24/2009 |
| 20090267052 | LAYER TRANSFER OF LOW DEFECT SiGe USING AN ETCH-BACK PROCESS A method for forming strained Si or SiGe on relaxed SiGe on insulator (SGOI) or a SiGe on Si heterostructure is described incorporating growing epitaxial Si1-yGey layers on a semiconductor substrate, smoothing surfaces by Chemo-Mechanical Polishing... | 10/29/2009 |
| 20090236587 | SEMICONDUCTOR DEVICE INCLUDING A PLURALITY OF DIFFERENT FUNCTIONAL ELEMENTS AND METHOD OF MANUFACTURING THE SAME At least first and second Si1-xGex (0≦x≦1) layers are formed on an insulating film. At least first and second material layers are formed correspondingly to the at least first and second Si1-xGex (0≦x≦1) layers. A latti... | 09/24/2009 |
| 20090173939 | Hybrid Wafers A hybrid wafer comprises a single-crystal SixGe1-x layer (15), where 0≦x≦1, a high thermal conductivity layer (10), and between the single-crystal SixGe1-x layer (15) and the high thermal conductivity ... | 07/09/2009 |
| 20090173933 | Thermal Sensor with a Silicon/Germanium Superlattice Structure A silicon/germanium (SiGe) superlattice thermal sensor is provided with a corresponding fabrication method. The method forms an active CMOS device in a first Si substrate, and a SiGe superlattice structure on a second Si-on-insulator (SOI) substrate. The first substrate... | 07/09/2009 |
| 20090134381 | Semiconductor device and fabrication method thereof A semiconductor device includes a gate electrode formed on a silicon substrate via a gate insulation film in correspondence to a channel region, source and drain regions of a p-type diffusion region formed in the silicon substrate at respective outer sides of sidewall i... | 05/28/2009 |
| 20090020748 | SI/SIGE INTERBAND TUNNELING DIODES WITH TENSILE STRAIN Some disclosed interband tunneling diodes comprise a plurality of substantially coherently strained layers including layers selected from a group consisting of silicon, germanium, and alloys of silicon and germanium, wherein at least one of said substantially coherently... | 01/22/2009 |
| 20080277647 | Materials and Optical Devices Based on Group IV Quantum Wells Grown on Si-Ge-Sn Buffered Silicon A semiconductor structure including a single quantum well Ge1−x1−ySix1Sn/Ge1−x2Six2 heterostructure grown strain-free on Si(100) via a Sn1−xGex buffer layer is shown.... | 11/13/2008 |
| 20080276979 | SEMICONDUCTOR NANOWIRE THERMOELECTRIC MATERIALS AND DEVICES, AND PROCESSES FOR PRODUCING SAME The present invention provides nanowires and nanoribbons that are well suited for use in thermoelectric applications. The nanowires and nanoribbons are characterized by a periodic longitudinal modulation, which may be a compositional modulation or a strain-induced modul... | 11/13/2008 |
| 20080246019 | DEFECT REDUCTION BY OXIDATION OF SILICON A method of fabricating high-quality, substantially relaxed SiGe-on-insulator substrate materials which may be used as a template for strained Si is described. A silicon-on-insulator substrate with a very thin top Si layer is used as a template for compressively straine... | 10/09/2008 |
| 20080237575 | Silicon germanium and germanium multigate and nanowire structures for logic and multilevel memory applications A method to provide a transistor or memory cell structure. The method comprises: providing a substrate including a lower Si substrate and an insulating layer on the substrate; providing a first projection extending above the insulating layer, the first projection includ... | 10/02/2008 |
| 20080182424 | METHOD FOR SELECTIVELY CONTROLLING LENGTHS OF NANOWIRES A method for selectively controlling lengths of nanowires in a substantially non-uniform array of nanowires includes establishing at least two different catalyzing nanoparticles on a substrate. A nanowire from each of the at least two different catalyzing nanoparticles ... | 07/31/2008 |
| 20080142785 | Strain-inducing semiconductor regions A method to form a strain-inducing semiconductor region is described. In one embodiment, formation of a strain-inducing semiconductor region laterally adjacent to a crystalline substrate results in a uniaxial strain imparted to the crystalline substrate, providing a str... | 06/19/2008 |
| 20080135830 | SEMICONDUCTOR STRUCTURES WITH STRUCTURAL HOMOGENEITY Semiconductor structures are formed with semiconductor layers having reduced compositional variation. Top surfaces of the semiconductor layers are substantially haze-free.... | 06/12/2008 |
| 20080099754 | METHOD FOR PROVIDING A NANOSCALE, HIGH ELECTRON MOBILITY TRANSISTOR (HEMT) ON INSULATOR A method and resulting high electron mobility transistor comprised of a substrate and a relaxed silicon-germanium layer formed over the substrate. A dopant layer is formed within the relaxed silicon-germanium layer. The dopant layer contains carbon and/or boron and has ... | 05/01/2008 |
| 20080078988 | Strained Si/SiGe/SOI islands and processes of making same A process of making a strained silicon-on-insulator structure is disclosed. A recess is formed in a substrate to laterally isolate an active area. An undercutting etch forms a bubble recess under the active area to partially vertically isolate the active area. A thermal... | 04/03/2008 |
| 20080078987 | UV-assisted dielectric formation for devices with strained germanium-containing layers A method of forming a semiconductor device includes providing a substrate in a vacuum processing tool, the substrate having a strained Ge-containing layer on the substrate and a Si-containing layer on the strained Ge-containing layer, maintaining the substrate at a temp... | 04/03/2008 |
| 20080067499 | Silicon/germanium superlattice thermal sensor A silicon/germanium (SiGe) superlattice thermal sensor is provided with a corresponding fabrication method. The method forms an active CMOS device in a first Si substrate, and a SiGe superlattice structure on a second Si-on-insulator (SOI) substrate. The first substrate... | 03/20/2008 |
| 20080054250 | Structure and methods for forming SiGe stressors A semiconductor structure includes a semiconductor substrate; a gate stack on the semiconductor substrate; a stressor having at least a portion in the semiconductor substrate and adjacent to the gate stack, wherein the stressor comprises an impurity of a first conductiv... | 03/06/2008 |
| 20080048175 | Semiconductor superjunction structure Semiconductor structures and methods are provided for a semiconductor device (54-11, 54-12) employing a superjunction structure (81). The method comprises, forming (52-6) first spaced-apart regions (70-1, 70-2, ... | 02/28/2008 |
| 20080042123 | Methods for controlling thickness uniformity of SiGe regions An integrated circuit includes a semiconductor substrate having a first region, at least one p-type region in the semiconductor substrate having SiGe regions formed therein, and at least one n-type region in the semiconductor substrate. All SiGe regions in the first reg... | 02/21/2008 |
| 20080042124 | Semiconductor device and method for manufacturing the same A semiconductor device and a method for manufacturing the same are disclosed, in which an insulating layer may be formed in a strained silicon layer under source/drain regions to substantially overcome conventional problems resulting from a channel decrease in the semic... | 02/21/2008 |
| 20080023692 | TRANSISTOR HAVING A STRAINED CHANNEL REGION INCLUDING A PERFORMANCE ENHANCING MATERIAL COMPOSITION By forming a semiconductor alloy in a silicon-based active semiconductor region prior to the gate patterning, material characteristics of the semiconductor alloy itself may also be exploited in addition to the strain-inducing effect thereof. Consequently, device perform... | 01/31/2008 |
| 20080006818 | STRUCTURE AND METHOD TO FORM MULTILAYER EMBEDDED STRESSORS A multilayer embedded stressor having a graded dopant profile for use in a semiconductor structure for inducing strain on a device channel region is provided. The inventive multilayer stressor is formed within areas of a semiconductor structure in which source/drain reg... | 01/10/2008 |
| 20070295953 | Germanium phototransistor with floating body A floating body germanium (Ge) phototransistor and associated fabrication process are presented. The method includes: providing a silicon (Si) substrate; selectively forming an insulator layer overlying the Si substrate; forming an epitaxial Ge layer overlying the insul... | 12/27/2007 |
| 20070290192 | Method to prevent defects on SRAM cells that incorporate selective epitaxial regions An SRAM device and method of forming MOS transistors of the device having reduced defects associated with selective epitaxial growth in moat tip regions is discussed. The SRAM device comprises a core region and a logic region, logic transistors within the logic region o... | 12/20/2007 |
| 20070262295 | A METHOD FOR MANIPULATION OF OXYGEN WITHIN SEMICONDUCTOR MATERIALS Methods and electronic devices fabricated by those methods are disclosed where the method allows controlled movement of oxygen during fabrication of electronic and photonic devices, facilitated by a technique of oxygen updiffusion (OUD). The method includes fabrication ... | 11/15/2007 |
| 20070262296 | Photodetectors employing germanium layers A germanium-based photodetector comprises a p- (or n-type) germanium layer, an intrinsic single crystal germanium layer formed on the p- (or n-) type germanium layer, and an n- (or p-type) germanium layer formed on the intrinsic single crystal germanium layer. An electr... | 11/15/2007 |
| 20070257301 | MULTI-GATE FET WITH MULTI-LAYER CHANNEL The invention concerns a field-effect transistor with a drain, a source, a channel in electrical contact with the source and the drain, and at least one gate, so as to apply an electric field to the channel when each gate is polarised, where the channel has a multi-laye... | 11/08/2007 |
| 20070257249 | SILICON/SILCION GERMANINUM/SILICON BODY DEVICE WITH EMBEDDED CARBON DOPANT A semiconductor structure and method of manufacturing a semiconductor device, and more particularly, an NFET device. The devices includes a stress receiving layer provided over a stress inducing layer with a material at an interface there between which reduces the occur... | 11/08/2007 |
| 20070241323 | Trench-edge-defect-free recrystallization by edge-angle-optimized solid phase epitaxy: method and applications to hybrid orientation substrates Edge-angle-optimized solid phase epitaxy is described as a method for forming hybrid orientation substrates comprising changed-orientation Si device regions free of the trench-edge defects typically seen when trench-isolated regions of Si are recrystallized to the orien... | 10/18/2007 |
| 20070228357 | TECHNIQUE FOR PROVIDING STRESS SOURCES IN MOS TRANSISTORS IN CLOSE PROXIMITY TO A CHANNEL REGION A strained semiconductor material may be positioned in close proximity to the channel region of a transistor, such as an SOI transistor, while reducing or avoiding undue relaxation effects of metal silicides and extension implantations, thereby providing enhanced effici... | 10/04/2007 |
| 20070215859 | Strained silicon with elastic edge relaxation A thin blanket epitaxial layer of SiGe is grown on a silicon substrate to have a biaxial compressive stress in the growth plane. A thin epitaxial layer of silicon is deposited on the SiGe layer, with the SiGe layer having a thickness less than its critical thicknesses. ... | 09/20/2007 |
| 20070205408 | Microstructure for formation of a silicon and germanium on insulator substrate of Si1-XGeX type The microstructure is designed for formation of a silicon and germanium on insulator substrate of Si1-XfGeXf type, with Xf comprised between a first value that is not zero and 1. The microstructure is formed by stacking of a silicon on insulator su... | 09/06/2007 |
