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| Number | Title | Issue Date |
| 8179455 | Optical black-level cancellation for optical sensors using open-loop sample calibration amplifier A Optical Black Pixel (OBP) cancellation circuit corrects offsets in sensors in a CCD/CMOS image sensor when reading dark pixels such at the periphery. A pixel voltage is switched to a sampling capacitor during two phases of the same pixel pulse. Sampling capacitors... | 05/15/2012 |
| 7965546 | Synchronous page-mode phase-change memory with ECC and RAM cache Phase-change memory (PCM) cells store data using alloy resistors in high-resistance amorphous and low-resistance crystalline states. The time of the memory cell's set-current pulse can be 100 ns, much longer than read or reset times. The write time thus depends on t... | 06/21/2011 |
| 7904655 | Branching memory-bus module with multiple downlink ports to standard fully-buffered memory modules A branching memory-bus module has one uplink port and two or more downlink ports. Frames sent downstream by a host processor are received on the uplink port and repeated to the multiple downlink ports to two or more branches of memory modules. Frames sent upstream t... | 03/08/2011 |
| 7865630 | Single-chip multi-media card/secure digital (MMC/SD) controller reading power-on boot code from integrated flash memory for user storage A Multi-Media Card/Secure Digital (MMC/SD) single-chip flash device contains a MMC/SD flash microcontroller and flash mass storage blocks containing flash memory arrays that are block-addressable rather than randomly-addressable. MMC/SD transactions from a host MMC/... | 01/04/2011 |
| 7813158 | Recordable electrical memory A memory device includes memory cells each having a recordable layer between two metal layers, each memory cell being constructed and designed to change from a first state to a second state upon application of an initialization signal, and change from the second sta... | 10/12/2010 |
| 7797583 | Fault diagnosis of serially-addressed memory modules on a PC motherboard A test adaptor board connects to a personal computer (PC) motherboard that tests a memory module in a test socket. A standard memory module socket is removed from a target DRAM module slot on the component side and the test adaptor board connects to the target DRAM ... | 09/14/2010 |
| 7797578 | Fault diagnosis of serially-addressed memory chips on a test adaptor board to a middle memory-module slot on a PC motherboard A standard memory module socket is removed from a target DRAM module slot on the component side and the test adaptor board connects to the target DRAM module slot on the reverse (solder) side of a personal computer motherboard, or an extender card may be used. The t... | 09/14/2010 |
| 7746087 | Heating-control isolation-diode temperature-compensation A semiconductor integrated circuit (IC) acts as a controller of a heating-controlled device or appliance. A heating body has a positive temperature coefficient and acts as both a heating element and a temperature sensor. A Silicon-Controlled Rectifier (SCR) switches... | 06/29/2010 |
| 7741981 | Dual-use comparator/op amp for use as both a successive-approximation ADC and DAC A re-configurable circuit acts as an Analog-to-Digital Converter (ADC) and as a digital-to-analog converter (DAC). An array of binary-weighted capacitors stores an analog input. Switches connect different capacitors in the array to fixed voltages that cause charge-s... | 06/22/2010 |
| 7657692 | High-level bridge from PCIE to extended USB An extended universal-serial bus (EUSB) bridge to a host computer can have peripheral component interconnect express (PCIE) protocol layers on one side of the bridge, and EUSB layers on the other side of the bridge, with a high-level bridging converter module connec... | 02/02/2010 |
| 7649743 | Open-frame solid-state drive housing with intrinsic grounding to protect exposed chips An open-frame flash-memory drive has a printed-circuit board assembly (PCBA) with flash-memory chips, a controller chip, and a Serial AT-Attachment (SATA) connector soldered to it. The PCBA is only partially encased by left and right frames or by a U-shaped bracket ... | 01/19/2010 |
| 7649742 | Thin flash-hard-drive with two-piece casing A flash-memory drive replaces a hard-disk drive using an integrated device electronics (IDE) interface. The flash drive has a printed-circuit board assembly (PCBA) with a circuit board with flash-memory chips and a controller chip. The controller chip includes an in... | 01/19/2010 |
| 7620769 | Recycling partially-stale flash blocks using a sliding window for multi-level-cell (MLC) flash memory A sliding window of flash blocks is used to reduce wasted space occupied by stale data in a flash memory. The sliding window slides downward over a few flash blocks. The oldest block is examined for valid pages of data, and the valid pages are copied to the end of t... | 11/17/2009 |
| 7619938 | Repairing advanced-memory buffer (AMB) with redundant memory buffer for repairing DRAM on a fully-buffered memory-module A repairing fully-buffered memory module can have memory chips with some defects such as single-bit errors. A repair controller is added to the Advanced Memory Buffer (AMB) on the memory module. The AMB fully buffers memory requests that are sent as serial packets o... | 11/17/2009 |
| 7576990 | Thin hard drive with 2-piece-casing and ground pin standoff to reduce ESD damage to stacked PCBA's A case-grounded flash-memory drive has a printed-circuit board assembly (PCBA) with flash-memory chips and a controller chip. The PCBA is encased inside an upper case and a lower case, with a Serial AT-Attachment (SATA) connector that fits through and opening betwee... | 08/18/2009 |
| 7535272 | Zero-delay buffer with common-mode equalizer for input and feedback differential clocks into a phase-locked loop (PLL) A zero-delay clock generator has a phase-locked loop (PLL) that generates a feedback clock and receives a reference clocks. All clocks are differential and have a common-mode voltage. The common-mode voltage of an externally-generated reference clock can vary from t... | 05/19/2009 |
| 7535088 | Secure-digital (SD) flash card with slanted asymmetric circuit board A flash-memory device has a printed-circuit board assembly (PCBA) with a PCB with a flash-memory chip and a controller chip. The controller chip includes an input/output interface circuit to an external computer over a Secure-Digital (SD) interface, and a processing... | 05/19/2009 |
| 7485007 | Swiveling offset adapter dongle for reducing blockage of closely-spaced video connectors A swivel adapter connects plugs for different video-connector standards. A smaller Display-Port (DP) connector fits into ports on a personal computer or other device, while a larger Digital Visual Interface (DVI) connector connects to a display or other device throu... | 02/03/2009 |
| 7487428 | Fully-buffered memory-module with error-correction code (ECC) controller in serializing advanced-memory buffer (AMB) that is transparent to motherboard memory controller An error-correcting fully-buffered memory module can detect and correct some errors in data read from memory chips. An error correction code ECC controller is added to the Advanced Memory Buffer (AMB) on the memory module that fully buffers memory requests sent as s... | 02/03/2009 |
| 7483824 | Self-checking test generator for partially-modeled processors by propagating fuzzy states A self-checking test generator program creates a self-checking test program that can test a device under test (DUT). The self-checking test generator selects instructions for a test. Selected instructions are executed on a software DUT model to generate results that... | 01/27/2009 |
| 7476105 | Super-digital (SD) flash card with asymmetric circuit board and mechanical switch A flash-memory device has a printed-circuit board assembly (PCBA) with a PCB with a flash-memory chip and a controller chip. The controller chip includes an external Secure-Digital (SD) interface, and a processing unit to read blocks of data from the flash-memory ch... | 01/13/2009 |
| 7478290 | Testing DRAM chips with a PC motherboard attached to a chip handler by a solder-side adaptor board with an advanced-memory buffer (AMB) Memory chips are tested by insertion into a chip test socket on a test adapter board that is mounted to the reverse or solder-side of a personal computer motherboard. A memory module socket is removed from the motherboard, and adapter pins are inserted into holes fo... | 01/13/2009 |
| 7474576 | Repairing Advanced-Memory Buffer (AMB) with redundant memory buffer for repairing DRAM on a fully-buffered memory-module A repairing fully-buffered memory module can have memory chips with some defects such as single-bit errors. A repair controller is added to the Advanced Memory Buffer (AMB) on the memory module. The AMB fully buffers memory requests that are sent as serial packets o... | 01/06/2009 |
| 7437597 | Write-back cache with different ECC codings for clean and dirty lines with refetching of uncorrectable clean lines A write-back cache has error-correction code (ECC) fields storing ECC bits for cache lines. Clean cache lines are re-fetched from memory when an ECC error is detected. Dirty cache lines are corrected using the ECC bits or signal an uncorrectable error. The type of E... | 10/14/2008 |
| 7391251 | Pre-emphasis and de-emphasis emulation and wave shaping using a programmable delay without using a clock An adjustable-delay filter performs wave shaping to emulate pre-emphasis or de-emphasis of transmission-line signals. The adjustable-delay filter uses analog components and does not need a clock. The receiver does not have to recover a bit-clock from the data stream... | 06/24/2008 |
| 7383362 | Single-chip multi-media card/secure digital (MMC/SD) controller reading power-on boot code from integrated flash memory for user storage A Multi-Media Card/Secure Digital (MMC/SD) single-chip flash device contains a MMC/SD flash microcontroller and flash mass storage blocks containing flash memory arrays that are block-addressable rather than randomly-addressable. MMC/SD transactions from a host MMC/... | 06/03/2008 |
| 7366847 | Distributed cache coherence at scalable requestor filter pipes that accumulate invalidation acknowledgements from other requestor filter pipes using ordering messages from central snoop tag A multi-processor, multi-cache system has filter pipes that store entries for request messages sent to a central coherency controller. The central coherency controller orders requests from filter pipes using coherency rules but does not track completion of invalidat... | 04/29/2008 |
| 7332929 | Wide-scan on-chip logic analyzer with global trigger and interleaved SRAM capture buffers A system chip has many local blocks including processor cores, caches, and memory controllers. Each local block has a local sample-select mux that is controlled by a local selection control register. The mux selects from among hundreds of internal sample nodes in th... | 02/19/2008 |
| 7333364 | Cell-downgrading and reference-voltage adjustment for a multi-bit-cell flash memory A flash memory has multi-level cells (MLC) that can each store multiple bits per cell. Blocks of cells can be downgraded to fewer bits/cell when errors occur, or for storing critical data such as boot code. The bits from a single MLC are partitioned among multiple p... | 02/19/2008 |
| 7332977 | Crystal clock generator operating at third overtone of crystal's fundamental frequency A crystal oscillator operates at the third overtone of the crystal's fundamental frequency. A value of a shunt resistor between the two phase-shift leg nodes is chosen so that the absolute value of the product gm×(Xc1)×(Xc2) is greater than the effec... | 02/19/2008 |
| 7307635 | Display rotation using a small line buffer and optimized memory access A frame buffer stores X pixels per line and Y lines and is read using a burst of B pixels. The un-rotated image is rotated by 90 degrees for display by writing and reading pixels from a line buffer. The line buffer stores a block of B*Y pixels. The frame buffer is l... | 12/11/2007 |
| 7308523 | Flow-splitting and buffering PCI express switch to reduce head-of-line blocking An enhanced Peripheral Component Interconnect Express (PCIe) switch eliminates or reduces head-of-line blocking for memory reads initiated by peripheral endpoint devices. A memory-read request packet from a first peripheral endpoint device is intercepted by the enha... | 12/11/2007 |
| 7289823 | Video overlay buffer mirrored through a shared mailbox between two processors in a feature phone A feature phone has two processors that share a display. The display is attached to an applications processor that has a frame buffer for refreshing the display. A base-band processor also runs programs that generate graphics data that is written to a base-band fram... | 10/30/2007 |
| 7277592 | Spacial deblocking method using limited edge differences only to linearly correct blocking artifact A de-blocking method smoothes pixels along a row or column that crosses a block boundary. Smoothing is performed to remove quantization or compression artifacts that appear on block edges when pixels in adjacent blocks are separately compressed. A maximum-allowed ed... | 10/02/2007 |
| 7272654 | Virtualizing network-attached-storage (NAS) with a compact table that stores lossy hashes of file names and parent handles rather than full names Multiple Network Attached Storage (NAS) appliances are pooled together by a virtual NAS translator, forming one common name space visible to clients. Clients send messages to the virtual NAS translator with a file name and a virtual handle of the parent directory th... | 09/18/2007 |
| 7265620 | Wide-band high-gain limiting amplifier with parallel resistor-transistor source loads An amplifier has a wide bandwidth and a high gain by using parallel loads. Each load has a load resistor and a load p-channel transistor in parallel. The drain voltages of differential n-channel transistors can be set by the load resistors, while switching current i... | 09/04/2007 |
| 7263642 | Testing replicated sub-systems in a yield-enhancing chip-test environment using on-chip compare to expected results for parallel scan chains testing critical and repairable sections of each sub-system A multi-processor chip has several processor cores that are simultaneously tested in parallel. The processor cores each have identical scan chains that produce identical test results absent defects. Expected test data is scanned from an external tester onto the chip... | 08/28/2007 |
| 7246434 | Method of making a surface mountable PCB module A printed-circuit board (PCB) module has co-planar solder pads on a bottom surface. The solder pads can be surface-mounted to pads on a main board, allowing the PCB module to be surface mounted without wire leads extending from the PCB module substrate. A cavity is ... | 07/24/2007 |
| 7225300 | Duplicate snoop tags partitioned across multiple processor/cache chips in a multi-processor system Several cluster chips and a shared main memory are connected by interconnect buses. Each cluster chip has multiple processors using multiple level-2 local caches, two memory controllers and two snoop tag partitions. The interconnect buses connect all local caches to... | 05/29/2007 |
| 7221727 | All-digital phase modulator/demodulator using multi-phase clocks and digital PLL Multi-phase clocks are used to encode and decode signals that are phase-modulated. The input signal is phase-compared with a feedback clock. Phase differences increment or decrement an up/down counter. The count value from the up/down counter is applied to a phase r... | 05/22/2007 |
