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| Number | Title | Issue Date |
| 8069356 | Accessory power management Methods, apparatus, and circuits for managing power among portable computing devices and one or more accessories. One example provides commands to improve power management between a portable computing device and one or more accessories. Other examples provide comman... | 11/29/2011 |
| 7809904 | Page preloading using page characterization data Circuits, methods, and apparatus that pre-load data that may be needed by a graphics processor to render upcoming scenes. One example determines one or more possible upcoming scenes or views. To save computing resources, the possible upcoming scenes are not fully re... | 10/05/2010 |
| 7725755 | Self-compensating delay chain for multiple-date-rate interfaces Methods and apparatus for delaying a clock signal for a multiple-data-rate interface. An apparatus provides an integrated circuit including a frequency divider configured to receive a first clock signal and a first variable-delay block configured to receive an outpu... | 05/25/2010 |
| 7697009 | Processing high numbers of independent textures in a 3-D graphics pipeline Circuits, methods, and apparatus provide for the storage of texture descriptors in a graphics memory. Since the texture descriptors are stored in a graphics memory, they do not need to be stored in the graphics processor itself, thus reducing graphics processor circ... | 04/13/2010 |
| 7675336 | Clock duty cycle recovery circuit Circuits, methods, and apparatus that provide the improvement or recovery of a duty cycle of a clock signal. One embodiment of the present invention receives a clock signal that may have a degraded duty cycle. The frequency of the clock signal is divided by two. The... | 03/09/2010 |
| 7671776 | Input sampling network that avoids undesired transient voltages Circuits, methods, and apparatus that provide sampling networks that avoid undesired transient voltages. One example provides a sampling network that includes a switch such that charge is transferred to an integrator in two separate steps instead of one. This switch... | 03/02/2010 |
| 7663621 | Cylindrical wrapping using shader hardware Circuits, methods, and apparatus that perform cylindrical wrapping in software without the need for a dedicated hardware circuit. One example performs cylindrical wrapping in software running on shader hardware. In one specific example, the shader hardware is a unif... | 02/16/2010 |
| 7657775 | Dynamic memory clock adjustments Methods, circuits, and apparatus for changing a frequency of a clock signal provided to a graphics memory while reducing any resulting visual glitch or disturbance on a monitor. A specific embodiment provides multiple clock sources that may be multiplexed or selecte... | 02/02/2010 |
| 7649538 | Reconfigurable high performance texture pipeline with advanced filtering Circuits, methods, and apparatus that provide texture caches and related circuits that store and retrieve texels in a fast and efficient manner. One such texture circuit provides an increased number of bilerps for each pixel in a group of pixels, particularly when t... | 01/19/2010 |
| 7590008 | PVT compensated auto-calibration scheme for DDR3 Circuits, methods, and apparatus that provide the calibration of input and output circuits for a high-speed memory interface. Timing errors caused by the fly-by routing of a clock signal provided by the memory interface are calibrated for both read and write paths. ... | 09/15/2009 |
| 7586341 | Programmable high-speed interface Methods and apparatus for providing either high-speed, or lower-speed, flexible inputs and outputs. An input and output structure having a high-speed input, a high-speed output, a low or moderate speed input, and an low or moderate speed output is provided. One of t... | 09/08/2009 |
| 7573297 | Flexible macrocell interconnect Methods and apparatus for novel routing structures and methods that improve fitting of user-defined functions onto programmable logic devices. In particular, second time fitting is improved. Exemplary structures and methods include allowing product terms to be expan... | 08/11/2009 |
| 7565490 | Out of order graphics L2 cache Circuits, methods, and apparatus that provide an L2 cache that services requests out of order. This L2 cache processes requests that are hits without waiting for data corresponding to requests that are misses to be returned from a graphics memory. A first auxiliary ... | 07/21/2009 |
| 7546424 | Embedded processor with dual-port SRAM for programmable logic Methods and apparatus for programmable logic devices including embedded processors having a dual-port SRAMs. A programmable logic integrated circuit includes a programmable logic portion having a plurality of logic elements, programmably configurable to implement us... | 06/09/2009 |
| 7519781 | Physically-based page characterization data Circuits, methods, and apparatus for efficiently storing page characteristics. Page characteristics for memory pages are stored post address translation using addresses for physical locations in memory, for example, in a bit vector. The characteristics may include a... | 04/14/2009 |
| 7502264 | On-chip EE-PROM programming waveform generation Circuits, methods, and apparatus that provide waveforms having controlled rise and fall times, as well as accurate peak voltages. One embodiment provides circuitry for generating a clock signal and a current that are adjusted for an on-chip capacitance variation. Th... | 03/10/2009 |
| 7498852 | Phase error correction circuit for a high speed frequency synthesizer Circuits, methods, and apparatus for adjusting an NCO output in order to provide a signal that is phase-locked to a reference signal. This is particularly beneficial where the frequencies of the NCO output and reference signal are unrelated. One embodiment provides ... | 03/03/2009 |
| 7487681 | Pressure sensor adjustment using backside mask Methods and apparatus for an absolute or gauge pressure sensor having a backside cavity with a substantially vertical interior sidewall. The backside cavity is formed using a DRIE etch or other MEMS micro-machining technique. The backside cavity has an opening that ... | 02/10/2009 |
| 7483032 | Zero frame buffer Circuits, methods, and apparatus that allow the elimination of a frame buffer connected directly to a graphics processing unit. The graphics processing unit includes an on-chip memory. Following system power-up or reset, the GPU initially renders comparatively low-r... | 01/27/2009 |
| 7479965 | Optimized alpha blend for anti-aliased render Circuits, methods, and apparatus that reduce the amount of data transferred between a graphics processor integrated circuit and graphics memory. Various embodiments of the present invention further improve the efficiency of blenders that are included on a graphics p... | 01/20/2009 |
| 7477091 | Defect tolerant redundancy Circuits, methods, and apparatus for using redundant circuitry on integrated circuits in order to increase manufacturing yields. One exemplary embodiment of the present invention provides a circuit configuration wherein functional circuit blocks in a group of circui... | 01/13/2009 |
| 7478189 | Deadlock avoidance in a bus fabric Circuits, apparatus, and methods for avoiding deadlock conditions in a bus fabric. One exemplary embodiment provides an address decoder for determining whether a received posted request is a peer-to-peer request. If it is, the posted request is sent as a non-posted ... | 01/13/2009 |
| 7456833 | Graphical representation of load balancing and overlap Circuits, methods, and apparatus for graphically displaying performance metrics of processors such as graphics processing units in multiple processor systems. Embodiments of the present invention may provide metric information regarding operations in alternate-frame... | 11/25/2008 |
| 7443389 | Pixel clock spread spectrum modulation Circuits, methods, and apparatus that reduce the peak or maximum EMI generated by video signals provided to a CRT or digital display monitor. One exemplary embodiment provides for spreading the spectrum of the video signal in order to spread or diffuse its peak spec... | 10/28/2008 |
| 7406134 | Very high data rate up-conversion in FPGAs Methods, circuits, and apparatus for providing an RF up-converter using digital circuits. One exemplary embodiment provides an up-converter that uses multiple channels of parallel digital processing, then serializes individual bits from these channels to achieve hig... | 07/29/2008 |
| 7406564 | Distributed FIFO Circuits, methods, and apparatus for FIFO memories made up of multiple local memory arrays. These embodiments limit the number and length of interconnect lines that are necessary to join two or more local memory arrays into a single, larger functional unit. One exem... | 07/29/2008 |
| 7376803 | Page stream sorter for DRAM systems Circuits, methods, and apparatus for reordering memory access requests in a manner that reduces the number of page misses and thus increases effective memory bandwidth. An exemplary embodiment of the present invention uses an exposed FIFO structure. This FIFO is an ... | 05/20/2008 |
| 7362187 | Sequential VCO phase output enabling circuit Circuits, methods, and apparatus that provide a sequential start-up of outputs of an oscillator following a power-up or restart. The outputs are gated by enable signals. These enable signals are derived sequentially, the first in a series being triggered by a specif... | 04/22/2008 |
| 7342590 | Screen compression Methods, circuits, and apparatus for reducing memory bandwidth used by a graphics processor. Uncompressed tiles are read from a display buffer portion of a graphics memory and received by an encoder. The uncompressed tiles are compressed and written back to the grap... | 03/11/2008 |
| 7324405 | DQS postamble filtering Circuits, methods, and apparatus for filtering signals at a high-speed data interface. One exemplary embodiment is particularly configured to filter a clock signal at the end of a data burst received by a double-data rate memory interface. A clock input port is eith... | 01/29/2008 |
| 7315188 | Programmable high speed interface Methods and apparatus for providing either high-speed, or lower-speed, flexible inputs and outputs. An input and output structure having a high-speed input, a high-speed output, a low or moderate speed input, and an low or moderate speed output is provided. One of t... | 01/01/2008 |
| 7315912 | Deadlock avoidance in a bus fabric Circuits, apparatus, and methods for avoiding deadlock conditions in a bus fabric. One exemplary embodiment provides an address decoder for determining whether a received posted request is a peer-to-peer request. If it is, the posted request is sent as a non-posted ... | 01/01/2008 |
| 7315957 | Method of providing a second clock while changing a first supplied clock frequency then supplying the changed first clock Methods, circuits, and apparatus for changing a frequency of a clock signal provided to a graphics memory while reducing any resulting visual glitch or disturbance on a monitor. A specific embodiment provides multiple clock sources that may be multiplexed or selecte... | 01/01/2008 |
| 7295040 | High speed IO buffer using auxiliary power supply Circuits, methods, and apparatus that provide output drivers that consume relatively little integrated circuit area and provide fast output switching. An exemplary embodiment provides an output driver including pull-up and pull-down devices, each device driven by a ... | 11/13/2007 |
| 7289539 | Synchronization of stereo glasses in multiple-end-view environments Methods and apparatus for synchronizing a stereo viewing device in a multiple end-view environment. Two or more video streams and a corresponding number of signals, each synchronous with one of the video streams, are provided. Each of the video streams may have a di... | 10/30/2007 |
| 7259606 | Data sampling clock edge placement training for high speed GPU-memory interface Circuits, methods, and apparatus for training a phase shift circuit to provide a phase shift for improved data recovery. A specific embodiment of the present invention provides a variable delay cell. A delay through the variable delay cell is changed while training ... | 08/21/2007 |
| 7245302 | Processing high numbers of independent textures in a 3-D graphics pipeline Circuits, methods, and apparatus provide for the storage of texture descriptors in a graphics memory. Since the texture descriptors are stored in a graphics memory, they do not need to be stored in the graphics processor itself, thus reducing graphics processor circ... | 07/17/2007 |
| 7234069 | Precise phase shifting using a DLL controlled, multi-stage delay chain Circuits, methods, and apparatus that provide a precise phase shift for a read strobe or other signal. One embodiment provides a read strobe delay line including a series of delay elements, where inputs or outputs of at least some of delay elements are received by a... | 06/19/2007 |
| 7233334 | Storage buffers with reference counters to improve utilization Accordingly, embodiments of the present invention provide circuits, methods, and apparatus that improve utilization of storage buffers by overwriting data in them as soon as the data is no longer needed. An exemplary embodiment employs a counter to add each time a p... | 06/19/2007 |
| 7231536 | Control circuit for self-compensating delay chain for multiple-data-rate interfaces Circuits, methods, and apparatus that prevent control signals from changing state while the control signals are being used to delay a read strobe signal. An exemplary embodiment of the present invention provides a control circuit that provides a plurality of control... | 06/12/2007 |
