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| Number | Title | Issue Date |
| 8153480 | Air cavity package for flip-chip According to an example embodiment, there is method (100) for manufacturing a semiconductor device in an air-cavity package. For a device die having an active surface, a lead frame is provided (5), the lead frame has a top-side surface and an under-sid... | 04/10/2012 |
| 7911057 | Bumpless flip-chip assembly with a complaint interposer contractor Consistent with an example embodiment, an integrated circuit device (IC) is assembled on a package substrate and encapsulated in a molding compound. There is a semiconductor die having a circuit pattern with contact pads. A package substrate having bump pad landings... | 03/22/2011 |
| 7825526 | Fine-pitch routing in a lead frame based system-in-package (SIP) device In an example embodiment, there is a package substrate (200) for mounting an integrated circuit (IC) device (205). The package substrate comprises an IC device placement area (290) surrounded by pad landings (215). For placing surface mou... | 11/02/2010 |
| 7790480 | Method for determining relative swing curve amplitude A process (300) is disclosed to measure predetermined wavelength reflectance spectra of a photo resist coated wafer (305,310,315,320) at a nominal thickness. After coating, the predetermined wavelength reflectance (325,330) is measured and the p... | 09/07/2010 |
| 7709954 | Redistribution layer for wafer-level chip scale package and method therefor In an example embodiment, there is a method for packaging an integrated circuit device (IC) having a circuit pattern (305) in a wafer-level chip-scale (WLCS) package (300). The method includes depositing a metal layer (5, 10, 15) on a first diel... | 05/04/2010 |
| 7670961 | Reduction of cracking in low-k spin-on dielectric films The present invention relates to a process that minimizes the cracking of low-k dielectric polymers. In an example embodiment, on a semiconductor substrate (200), there is a method of forming a composite dielectric disposed on a metal layer passivated with plasma de... | 03/02/2010 |
| 7623979 | Calibration of tester and testboard by golden sample In performing testing on Automatic Test Equipment (ATE) it is a challenge to accurately generate and measure RF (radio frequency) power. In an example embodiment, in a test apparatus used for measuring the input and output characteristics of an amplifier, there is a... | 11/24/2009 |
| 7566919 | Method to reduce seedlayer topography in BICMOS process A method for forming an epitaxial base layer in a bipolar device. The method comprises the steps of: providing a structure having a field isolation oxide region (12) adjacent to an active silicon region (10); forming a silicon nitride/silicon stack ( | 07/28/2009 |
| 7565591 | Testing of circuits with multiple clock domains Consistent with an example embodiment, the amount of time required for testing circuits that contain a plurality of different clock domains is reduced. According to the embodiment, during selection of the input test pattern to test logic circuits between a timing se... | 07/21/2009 |
| 7557741 | Overload detection unit with signal strength indicator to indicate an overload condition A device is for digitally processing an input signal that is susceptible to variations in signal strength. The signal (48) is analog to digital converted into a bitstream signal (47), the bitstream signal representing the input signal by consecutive di... | 07/07/2009 |
| 7556900 | Measuring the effect of flare on line width In photo-lithography, one may assess the effect of flare due to various exposure tools. In an example embodiment, in a photo-lithography process on a photo resist coated substrate, there is a method (600) for determining the effect of flare on line shortening... | 07/07/2009 |
| 7556893 | Self-compensating mark design for stepper alignment A system and method for fabricating integrated circuits using four fine alignment targets per stepper shot. The four alignment targets are disposed within the scribe line on each side of a four-sided stepper shot. The targets on opposites sides of the region are loc... | 07/07/2009 |
| 7550990 | Method and apparatus for testing integrated circuits for susceptibility to latch-up In an example embodiment, there is a test module for testing the susceptibility of an integrated circuit design to latch-up. The test module comprises a plurality of test blocks, connected in parallel. Each test block includes an injector block for applying a stress... | 06/23/2009 |
| 7539879 | Register file gating to reduce microprocessor power dissipation A circuit arrangement and method of controlling power dissipation utilize a register file (60) with power dissipation control capabilities through a banked register design coupled with enable logic (62, 82) that is configured to selectively disable unu... | 05/26/2009 |
| 7538444 | Wafer with optical control modules in exposure fields In a wafer (1) with a number of exposure fields (2), each of which exposure fields (2) comprising a number of lattice fields (3) with an IC (4) located therein, two groups (5, 7) of dicing paths (6, 8) are provided an... | 05/26/2009 |
| 7538337 | Nanowire semiconductor device Semiconductor devices may be fabricated using nanowires. In an example embodiment, a conductive gate may be used to control conduction along the nanowires, in which case one of the contacts is a drain and the other a source. The nanowires may be grown in a trench or... | 05/26/2009 |
| 7537969 | Fuse structure having reduced heat dissipation towards the substrate A fuse structure (100) suitable for incorporation in an integrated circuit presents a reduced thermal conduction footprint to the substrate (103). A patterned material stack (102) is formed on a substrate (103) and at least a portion of a... | 05/26/2009 |
| 7537939 | System and method for characterizing lithography effects on a wafer In the manufacture of semiconductors, it is often necessary to characterize the effect of line width and line width shape on yield. In an example embodiment, there is a method (200) for randomizing exposure conditions across a substrate. The method comprises ... | 05/26/2009 |
| 7528679 | Circuit arrangement for shifting the phase of an input signal and circuit arrangement for suppressing the mirror frequency Circuit arrangement for shifting the phase of an input signal, which circuit arrangement consists of two branches whose two output signals are 90° phase-shifted, and use of this phase shifter in a circuit arrangement for suppressing the mirror frequency. The filter... | 05/05/2009 |
| 7521740 | Semiconductor device comprising extensions produced from material with a low melting point A semiconductor device comprises a gate electrode (1) and a gate insulating layer (2) both surrounded by a spacer (3) and produced on a surface (S) of a substrate (100) of a first semiconductor material. The device also comprises a source... | 04/21/2009 |
| 7521323 | Method of fabricating a double gate field effect transistor device, and such a double gate field effect transistor device The present invention discloses a method of forming a double gate field effect transistor device, and such a device formed with the method. One starts with a semiconductor-on-insulator substrate, and forms a first gate, source, drain and extensions, and prepares the... | 04/21/2009 |
| 7519494 | Integrated circuit with signature computation The present invention relates to an integrated circuit (DEC V) for processing a plurality of data samples (P) of a data signal (I), wherein said integrated circuit is associated with a counter (CT) and comprises means (SIGN M) for computing a signature, said counter... | 04/14/2009 |
| 7519342 | Tunable tracking filter An integrated tuner circuit has an arbitrary IF (intermediate frequency) output. The tuner includes an integrated circuit with a fixed-frequency control loop and a matched external variable capacitance Ct, to achieve tracking of a tuned LC band-pass filte... | 04/14/2009 |
| 7515888 | Systems and method for a highly integrated, multi-mode tuner A method for adjusting the signal to noise ratio of a receiver comprises measuring the peak power for an RF signal and determining, based on the measured peak power, whether the RF signal power is within a desired operating range. The method further includes adjusti... | 04/07/2009 |
| 7514894 | Driver for a brushless motor and data reading/writing device comprising a brushless motor controlled by such a driver A driver for a brushless motor (10) is described comprising a static position sensing device (22), a back EMF detector for detecting a back EMF voltage (40), comprising a filter (42). The driver further comprises an output stage (30 | 04/07/2009 |
| 7514801 | Electronic device and method of manufacturing thereof The device has a carrier and an electric element. The carrier has a first and an opposed side and is provided with a connection layer, an intermediate layer and contact pads. The element is present at the first side and coupled to the connection layer. The element i... | 04/07/2009 |
| 7506227 | Integrated circuit with embedded identification code An integrated circuit (100) has a plurality of inputs (110) and a plurality of outputs (120). In a test mode, a test arrangement including a plurality of logic gates (140) is coupled between the plurality of inputs (110) and the pl... | 03/17/2009 |
| 7504971 | Decoding systems and methods Various embodiments of decoding systems and methods are disclosed. One system embodiment, among others, comprises a macroblock decode module configured to decode a plurality of context adaptive binary arithmetic coding (CABAC) encoded symbols corresponding to a slic... | 03/17/2009 |
| 7504853 | Arrangement for compensation of ground offset in a data bus system A description is given of an arrangement for compensation of ground offset in a data bus system comprising a plurality of communication devices (2, 10) which are each supplied with an operating voltage (U0) by a voltage source (4; 14), are conne... | 03/17/2009 |
| 7504846 | Testable cascode circuit and method for testing the same using a group of switching elements The cascode circuit comprises a plurality of switching transistors (11) to be protected from high voltage and a plurality of cascode transistors (13) connected to the switching transistors (11). A test node (B′) is arranged between each switch... | 03/17/2009 |
| 7504690 | Power semiconductor devices A vertical insulated gate field effect power transistor (3) has a plurality of parallel transistor cells (TC3) with a peripheral gate structure (G31, G2) at the boundary between each two transistor cells (TC3). The gate structure (... | 03/17/2009 |
| 7504307 | Semiconductor devices including voltage-sustaining space-charge zone and methods of manufacture thereof There is a method of manufacturing a semi conductor device that comprises source and drain regions of a first conductivity type, and a channel-accommodating region of a second, opposite conductivity type which separates the source and drain regions. The device compr... | 03/17/2009 |
| 7500126 | Arrangement and method for controlling power modes of hardware resources A circuit arrangement, method of executing program code and method of generating program code utilize power control instructions (90) capable of dynamically controlling power dissipation of multiple hardware resources (50-60) during execution of... | 03/03/2009 |
| 7492465 | Method for determining optimal resist thickness In an example embodiment, there is a method (600) for determining an approximately optimal resist thickness comprising providing a first substrate coated with a resist film having a first thickness using a first coat program, (605, 610). The first thic... | 02/17/2009 |
| 7491616 | Method of manufacturing a semiconductor device including dopant introduction The invention relates to a method of manufacturing a semiconductor device (10) in which a semiconductor body (1) of silicon is provided, at a surface thereof, with a semiconductor region (4) of a first conductivity type, in which region a second... | 02/17/2009 |
| 7492150 | Circuit arrangement method for obtaining an output signal, and rotational speed measurement device comprising such a circuit arrangement A circuit arrangement for obtaining an output signal (Va) form a signal (Vs) containing at least one alternating component comprises a signal source (1) that supplies this signal (Vs), a first peak value detection device (2) for determining a maximum v... | 02/17/2009 |
| 7492211 | Output driver equipped with a sensing resistor for measuring the current in the output driver An electronic circuit has an output driver (DRV) for providing a driving signal (U0). The output driver has a transistor (T) with a first main terminal, a second main terminal and a control terminal coupled to receive a control signal (Vcntrl),... | 02/17/2009 |
| 7492249 | Electronic communication system In order to develop an electronic communication system (100; 100′), designed for a progressive movement means, having at least one base station (10) and having at least one carrier station (60) such that the possible uses of this communication... | 02/17/2009 |
| 7493542 | Arrangement for testing integrated circuits The invention relates to an arrangement for testing integrated circuits, to a test system (2), to a circuit (1) to be tested, and to a method of testing logic circuits, where the test system (2) includes a programmable algorithmic test vector ge... | 02/17/2009 |
| 7493408 | USB host protocol A method of transferring bulk and control data from a first device to a second device over a USB bus comprises storing transfer descriptors, each including a transfer descriptor header and payload data, in a buffer memory in the first device. The data is read in pac... | 02/17/2009 |
