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| Number | Title | Issue Date |
| 6690676 | Non-addressed packet structure connecting dedicated end points on a multi-pipe computer interconnect bus The protocol of a multi-pipe interconnection bus includes the ability to send a non-addressed read or write transaction request over one of the pipes of a multiple-pipe computer interconnect bus. The multiple pipes carry transactions on a packet multiplex... | 02/10/2004 |
| 6684372 | Method, system and computer product to translate electronic schematic files between computer aided design platforms Provided is a method, a system and a computer product to translate electronic schematic files between computer-aided software design tools. One embodiment of the invention includes converting source files, containing electronic schematic information, into... | 01/27/2004 |
| 6671796 | Converting an arbitrary fixed point value to a floating point value A method and apparatus are provided for performing efficient conversion operations between floating point and fixed point values on a general purpose processor. This is achieved by providing an instruction for converting a fixed point value fx into a floa... | 12/30/2003 |
| 6670843 | Method and apparatus for sensing a programming state of fuses A fuse cell circuit includes a first fuse and a first fuse sense circuit that senses a programming state of the first fuse and supplies an indication thereof. A sense control circuit includes a plurality of reference fuses and a second fuse sense circuit ... | 12/30/2003 |
| 6668322 | Access management system and method employing secure credentials A security architecture has been developed in which a single sign-on is provided. Session credentials are used to maintain continuity of a persistent session across multiple accesses to one or more information resources, and in some embodiments, across cr... | 12/23/2003 |
| 6665350 | Method and system for improved analog signal detection A method and system for improved detection of analog signals, where the analog signals may be composed of one or more analog frequencies. In the method and system, an analog signal is received. A stream of data samples is created from the analog signal. B... | 12/16/2003 |
| 6657488 | Offset correction and slicing level adjustment for amplifier circuits A slice and offset circuit is provided that uses a digital integrator in the feedback loop of the offset cancellation circuitry. A slice circuit receives an indication of a desired slice voltage and supplies a signal to specify the slice level, which is c... | 12/02/2003 |
| 6646581 | Digital-to-analog converter circuit incorporating hybrid sigma-delta modulator circuit An exemplary PLL circuit includes a VCO responsive to a plurality of sub-varactor control signals. A digital loop filter for the PLL digitally generates a varactor control word, which is digitally expanded into a plurality of digital values, each of which... | 11/11/2003 |
| 6633509 | Partial selection of passive element memory cell sub-arrays for write operations A memory array is subdivided into many sub-arrays which are separately selectable in groups, with each group containing one or more sub-arrays. The various data bits of a data set are physically spread out and mapped into a large number of associated sub-... | 10/14/2003 |
| 6630868 | Digitally-synthesized loop filter circuit particularly useful for a phase locked loop In a feedback system such as a PLL, the integrating function associated with a loop filter capacitor is instead implemented digitally and is easily implemented on the same integrated circuit die as the PLL. There is no need for either an external loop fil... | 10/07/2003 |
| 6618782 | Computer interconnection bus link layer A computer system that includes a first integrated circuit that has a plurality of first functions. The first integrated circuit is coupled to a second integrated circuit having a plurality of second functions via a communication link that includes a plur... | 09/09/2003 |
| 6615338 | Clustered architecture in a VLIW processor A Very Long Instruction Word (VLIW) processor has a clustered architecture including a plurality of independent functional units and a multi-ported register file that is divided into a plurality of separate register file segments, the register file segmen... | 09/02/2003 |
| 6609198 | Log-on service providing credential level change without loss of session continuity A security architecture has been developed in which a single sign-on is provided for multiple information resources. Rather than specifying a single authentication scheme for all information resources, the security architecture associates trust-level requ... | 08/19/2003 |
| 6601178 | System power management partitioned across a serial bus An indication is provided to a first integrated circuit that a wake-up event has occurred on an input terminal of a second integrated circuit where the first and second integrated circuit are coupled by a bus. The bus is initially in a reduced power consu... | 07/29/2003 |
| 6590426 | Digital phase detector circuit and method therefor In a feedback system such as a PLL, the integrating function associated with a loop filter capacitor is instead implemented digitally and is easily implemented on the same integrated circuit die as the PLL. There is no need for either an external loop fil... | 07/08/2003 |
| 6581111 | Out-of-order probing in an in-order system A command filter selectively forwards received commands to a command queue for in-order execution. If the received command is a probe response command or if probe response information is extracted.from other commands, the probe response is stored in a sto... | 06/17/2003 |
| 6580376 | Apparatus and method for decimating a digital input signal In a feedback system such as a PLL, the integrating function associated with a loop filter capacitor is instead implemented digitally and is easily implemented on the same integrated circuit die as the PLL. There is no need for either an external loop fil... | 06/17/2003 |
| 6564272 | Non-coherent cache buffer for read accesses to system memory A computer system includes a read ahead buffer coupled to a memory controller and an input/output controller coupled to an input/output channel. An I/O device provides an initial read request over the input/output channel which specifies an address in sys... | 05/13/2003 |
| 6556952 | Performance monitoring and optimizing of controller parameters An integrated circuit, system and method monitors parameter performance for optimization of controller performance. The integrated circuit includes a memory controller, one or more buffers coupled to the memory controller, and a performance monitoring cir... | 04/29/2003 |
| 6542990 | Array access boundary check by executing BNDCHK instruction with comparison specifiers The present invention provides a method and apparatus for executing a boundary check instruction that provides accelerated bound checking. The instruction can be used to determine whether an array address represents a null pointer, and whether an array in... | 04/01/2003 |
| 6542991 | Multiple-thread processor with single-thread interface shared among threads A processor includes logic for tagging a thread identifier (TID) for usage with processor blocks that are not stalled. Pertinent non-stalling blocks include caches, translation look-aside buffers (TLB), a load buffer asynchronous interface, an external me... | 04/01/2003 |
| 6532019 | Input/output integrated circuit hub incorporating a RAMDAC A computer system includes a first integrated circuit that has a central processing unit (CPU) and a graphics controller. An I/O hub, which is coupled to a plurality of input/output buses, includes a RAMDAC. An interconnect bus couples the first integrate... | 03/11/2003 |
| 6525949 | Charge pump circuit A charge pump circuit includes, in a preferred embodiment, a plurality of serially-connected pump stages, each of which is driven by one or more associated clock signals for the stage. The amplitude of the clock signals associated with a respective one of... | 02/25/2003 |
| 6523172 | Parser translator system and method A parser-translator technology allows a user to specify complex test and/or transformation statements in a high-level user language, to ensure that such test and/or transformation statements are well-formed in accordance with a grammar defining legal stat... | 02/18/2003 |
| 6523091 | Multiple variable cache replacement policy A method for selecting a candidate to mark as overwritable in the event of a cache miss while attempting to avoid a write back operation. The method includes associating a set of data with the cache access request, each datum of the set is associated with... | 02/18/2003 |
| 6523090 | Shared instruction cache for multiple processors The present invention provides a shared instruction cache for multiple processors. In one embodiment, an apparatus for a microprocessor includes a shared instruction cache for a first processor and a second processor, and a first register index base for t... | 02/18/2003 |
| 6522594 | Memory array incorporating noise detection line A memory array includes a sensing circuit for sensing bit line current while keeping the voltage of the selected bit line substantially unchanged. The word lines and bit lines are biased so that essentially no bias voltage is impressed across half-selecte... | 02/18/2003 |
| 6516349 | System for updating a set of instantiated content providers based on changes in content provider directory without interruption of a network information services A content provider manager has been develop for use in an information services such as a portal or desktop application to provide for "pluggable" content that may be modified simply through changes to the set of content provider components encoded in a re... | 02/04/2003 |
| 6515923 | Memory array organization and related test method particularly well suited for integrated circuits having write-once memory arrays In a preferred integrated circuit embodiment, a write-once memory array includes at least one test bit line which provides a respective test memory cell at the far end of each respective word line relative to its word line driver, and further includes at ... | 02/04/2003 |
| 6515501 | Signal buffers for printed circuit boards An improved signal buffer configuration has been developed for transmitting communication signals across line traces between ICs on a printed circuit board, printed wiring board, multi-chip module, integrated circuit carrier or package, or other interconn... | 02/04/2003 |
| 6515861 | Method and apparatus for shielding electromagnetic emissions from an integrated circuit A conductive plane of an integrated circuit package and a heatsink combine to form a structure for controlling electromagnetic emissions from the integrated circuit die that is mounted in the package. The heatsink includes a base and a projecting portion ... | 02/04/2003 |
| 6504753 | Method and apparatus for discharging memory array lines A passive element memory array preferably biases selected X-lines to an externally received VPP voltage and selected Y-lines to ground. Unselected Y-lines are preferably biased to VPP minus a first offset voltage, and unselected X-li... | 01/07/2003 |
| 6504865 | Digital connection detection technique A technique is described for reliably determining whether a direct digital connection exists between a transmitting server modem and a receiving client modem. Such a determination is an essential part of the training procedure for modems that conform to I... | 01/07/2003 |
| 6499079 | Subordinate bridge structure for a point-to-point computer interconnection bus A communication link is used both as a primary communication link and as a subordinate link in a computer system. A first integrated circuit having a plurality of first functions and a second integrated circuit having a plurality of second functions, are ... | 12/24/2002 |
| 6495396 | Method of coupling and aligning semiconductor devices including multi-chip semiconductor devices The present invention relates to semiconductor devices, including multi-chip semiconductor devices, and methods of coupling semiconductor devices. In a particular embodiment, the semiconductor device is a multi-chip semiconductor that comprises a first se... | 12/17/2002 |
| 6496383 | Integrated circuit carrier arrangement for reducing non-uniformity in current flow through power pins In an integrated circuit carrier having a large number of power pins allocated to an internal power plane, the current flowing through the power pins may divide very unevenly, and result in current flow through some of the power pins which exceeds the max... | 12/17/2002 |
| 6496572 | Call-waiting tone detection technique Reliable detection of a call-waiting tone is provided by employing a correlation based technique. A modem or other device employing such a technique need not rely on carrier drop detection and is generally insensitive to other energy or noise on the line.... | 12/17/2002 |
| 6490638 | General purpose bus with programmable timing A system provides a general purpose bus with programmable timing capability. As part of a microcontroller, this general purpose bus provides a mechanism for communication between general purpose peripherals connected to the bus and enables external device... | 12/03/2002 |
| 6489803 | Use of dual hysteresis modes in determining a loss of signal output indication A loss of signal condition is evaluated for an input data stream according to a signal strength threshold level. The signal strength threshold level is determined according to a supplied loss of signal (LOS) threshold level. Two hysteresis modes are used ... | 12/03/2002 |
| 6483728 | Charge pump circuit A charge pump circuit includes, in a preferred embodiment, a plurality of serially-connected pump stages, each of which is driven by one or more associated clock signals for the stage. The amplitude of the clock signals associated with a respective one of... | 11/19/2002 |
