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| Number | Title | Issue Date |
| 7346784 | Integrated circuit device programming with partial power A separate program power input is provided to a programmable logic array's memory to permit it to be programmed independently of printed circuit board power. Means are provided to isolate the program power input from the array's programmable logic circuit. Means are... | 03/18/2008 |
| 7200235 | Error-checking and correcting decryption-key memory for programmable logic devices Described are circuits that detect and correct for decryption key errors. In one example, a programmable logic device includes a decryption key memory with a number of decryption-key fields and, for each key field, an associated error-correction-code (ECC) field. Th... | 04/03/2007 |
| 7117373 | Bitstream for configuring a PLD with encrypted design data It is sometimes desirable to protect a design used in a PLD from being copied. If the design is stored in a different device from the PLD and read into the PLD through a bitstream, an unencrypted bitstream could be observed and copied as it is being loaded. Accordin... | 10/03/2006 |
| 7117372 | Programmable logic device with decryption and structure for preventing design relocation It is sometimes desirable to protect a design used in a PLD from being copied. According to the present invention, the design is encrypted, then loaded into a PLD, then decrypted, and then loaded into the configuration memory of the PLD. An attacker could relocate t... | 10/03/2006 |
| 7111273 | Softpal implementation and mapping technology for FPGAs with dedicated resources A softPAL implementation and mapping method are described. The implementation utilizes both LUTs and architecture-specific logic circuits to implement softPAL functions, and selects from several implementations in order to decrease delay in function implementation. ... | 09/19/2006 |
| 7100101 | Method and apparatus for concatenated and interleaved turbo product code encoding and decoding Method and apparatus for concatenated and interleaved turbo product code (TPC) encoding and decoding are described. Described are series concatenated and interleaved TPC encoders and decoders. One or more combinations of these encoders and decoders may be combined t... | 08/29/2006 |
| 7068072 | Integrated circuit with interface tile for coupling to a stacked-die second integrated circuit A general purpose interface tile of a first integrated circuit includes a plurality of micropads. A second integrated circuit may be stacked on the first integrated circuit such that signals from the second integrated circuit are communicated through the micropads a... | 06/27/2006 |
| 7062692 | Duty cycle characterization and adjustment Method and apparatus are described for duty cycle determination and adjustment. More particularly, an output signal is sampled and provided to duty cycle check circuitry which characterizes the duty cycle of the sampled output signal. This characterization may be pr... | 06/13/2006 |
| 7061102 | High performance flipchip package that incorporates heat removal with minimal thermal mismatch A semiconductor flipchip package includes a central cavity area on the first major side for receiving a flipchip die therein. The package substrate is substantially made from a single material that serves as the support and stiffener and provides within the cavity f... | 06/13/2006 |
| 7057413 | Large crossbar switch implemented in FPGA A method for using an FPGA to implement a crossbar switch is described. Rather than using signals routed through the general FPGA routing resources to control connectivity of the crossbar switch, the input signals only carry crossbar switch data, and the connectivit... | 06/06/2006 |
| 7058177 | Partially encrypted bitstream method It is sometimes desirable to encrypt a design for loading into a PLD so that an attacker may not learn and copy the design as it is being copied into the PLD. According to the invention, a method for generating a bitstream for storing an encrypted design begins by g... | 06/06/2006 |
| 7047467 | Structure and method for verifying data in a non-JTAG device from a JTAG device with microcontroller According to the invention, a JTAG-compliant chip having a controller that receives data provided on the TDI input pin and forms parallel address and data instructions and passes the data through IO pins to the non-JTAG chip is able to verify whether the data was co... | 05/16/2006 |
| 7047352 | Fail-safe method of updating a multiple FPGA configuration data storage system Structure and method for updating a system that includes a memory and a programmable logic device (PLD) retains a default PLD configuration in the memory while a new configuration is being stored in the memory, and thus protect the system from failure in case an int... | 05/16/2006 |
| 7036059 | Techniques for mitigating, detecting and correcting single event upset effects in systems using SRAM-based field programmable gate arrays SEU mitigation, detection, and correction techniques are disclosed. The mitigation techniques include: triple redundancy of a logic path is extended the length of the FPGA to avoid weak points susceptible to SEU effects; triple logic module and feedback redundancy p... | 04/25/2006 |
| 7023239 | Automated boundary-scan chain composition method using a device database and access mechanism for storing and retrieving situation-dependent operation options A method for programming a series of in-system programmable devices that uses Boundary-Scan techniques to read device identification codes from each device of a system, and to automatically generate a board/device information file including a record for each device ... | 04/04/2006 |
| 7020858 | Method and apparatus for producing a packaged integrated circuit A method of producing a wirebond ball grid array package is described. The method comprises the steps of importing a master pinlist to a computer program, importing a bonding diagram to the computer program, and verifying, by the computer program, substrate artwork ... | 03/28/2006 |
| 6984533 | Method of sorting dice by speed during die bond assembly and packaging to customer order When integrated circuit dice are tested as part of a completely manufactured wafer, the individual die is tested both for proper function and for speed grade. A wafer map is formed in a computer to keep up with which dice on the wafer are good and to record the spee... | 01/10/2006 |
| 6981153 | Programmable logic device with method of preventing readback It is sometimes desirable to protect a design used in a PLD from being copied. If the design is stored in a different device from the PLD and read into the PLD through a bitstream, the design may be encrypted as it is read into the PLD and decrypted within the PLD b... | 12/27/2005 |
| 6978427 | Literal sharing method for fast sum-of-products logic A method and apparatus for implementing fast sum-of-products logic in a field programmable gate array (FPGA) is disclosed. The method includes literal-sharing decomposition of the sum-of-products logic to reduce the number of configurable logic block (CLB) slices re... | 12/20/2005 |
| 6965675 | Structure and method for loading encryption keys through a test access port It is sometimes desirable to encrypt a design for loading into a PLD so that an attacker may not learn and copy the design as it is being written into the PLD. It is desirable that decryption keys be stored within the PLD, and that they be loaded conveniently before... | 11/15/2005 |
| 6963510 | Programmable capacitor and method of operating same A programmable capacitor in an integrated circuit (IC) comprises a conductive line located parallel to an interconnect. When a bias voltage is applied to the conductive line, a parasitic capacitance is created between the interconnect and the conductive line. By pro... | 11/08/2005 |
| 6963218 | Bi-directional interface and communication link Method and apparatus for a bi-direction interface and communication link are described. More particularly, an input/output block is formed with a digitally controlled impedance output driver output coupled at an input/output node to an input terminal of a differenti... | 11/08/2005 |
| 6957340 | Encryption key for multi-key encryption in programmable logic device It is sometimes desirable to protect a design used in a PLD from being copied. If the design is stored in a different device from the PLD and read into the PLD through a bitstream, an unencrypted bitstream could be observed and copied as it is being loaded. Accordin... | 10/18/2005 |
| 6932618 | Mezzanine integrated circuit interconnect An interconnect assembly to electrically interconnect one or more integrated circuits to an electronic device may comprise a base package to couple to a circuit board of the electronic device. A terminal mezzanine package may support the integrated circuit(s) above ... | 08/23/2005 |
| 6931543 | Programmable logic device with decryption algorithm and decryption key To prevent copying of a design implemented in a programmable logic device (PLD), the PLD itself stores a decryption key or keys loaded by the designer, and includes a decryptor for decrypting an encrypted configuration bitstream as it is loaded into the PLD. The PLD... | 08/16/2005 |
| 6925583 | Structure and method for writing from a JTAG device with microcontroller to a non-JTAG device According to the invention, a JTAG-compliant chip is further provided with a controller that receives data provided on the TDI input pin, forms parallel address and data instructions and passes the data through IO pins to the non-JTAG chip without requiring the data... | 08/02/2005 |
| 6914449 | Structure for reducing leakage current in submicron IC devices A technique for reducing leakage current in static CMOS devices by adding additional transistors in series between selected inverters or logic gates and ground or power. NMOS and PMOS transistors are added to selected buffers comprised of two inverters in series. Th... | 07/05/2005 |
| 6914804 | Memory cells enhanced for resistance to single event upset Method and apparatus are described for providing memory cells enhanced for resistance to single event upsets. In one embodiment, transistors are coupled between cross coupled inverters of a latch, thus in a small area providing both single-event-upset resistivity mo... | 07/05/2005 |
| 6904527 | Intellectual property protection in a programmable logic device Individual IP vendors can directly license their IP modules to PLD users. Each PLD has a unique device identifier (UDI). If a user obtains a license to use an IP module on a particular PLD, then the IP vendor issues the user an authorization code (AC). The user supp... | 06/07/2005 |
| 6904397 | System and method for assisting in the development and integration of reusable circuit designs A system and method for developing a reusable electronic circuit design module are presented in various embodiments. In one embodiment, the functional design elements comprising a design module are entered into a database along with documentation elements that descr... | 06/07/2005 |
| 6898776 | Method for concurrently programming a plurality of in-system-programmable logic devices by grouping devices to achieve minimum configuration time A method for concurrently programming a series of in-system devices by grouping the devices into sequentially-programmed groups, wherein a best possible grouping of devices is determined that achieves a minimum total configuration time. When a system includes multip... | 05/24/2005 |
| 6897676 | Configuration enable bits for PLD configurable blocks A programmable logic device (PLD) includes columns of block memory interposed between columns of configurable logic blocks (CLBs). Each column of block memory includes a plurality of random access memories (RAMs) that share common configuration address lines that do... | 05/24/2005 |
| 6895566 | Methods and apparatus for isolating critical paths on an IC device having a thermal energy generator Test methods and circuits isolate thermal effects from AC effects on circuit performance. Critical paths for a failing programmable logic device (PLD) are identified and tested. This testing minimizes the impact of power-supply flicker and noise by eliminating or in... | 05/17/2005 |
| 6891384 | Multi-socket board for open/short tester An interface structure includes first and second portions. The first portion has physical dimensions that are compatible with the docking area of an associated device tester, and includes a first socket configured to receive a first BGA package. The second portion, ... | 05/10/2005 |
| 6886152 | Delay optimization in signal routing A delay optimization algorithm has four major steps: (1) selecting signal connections to target for delay improvement; (2) unrouting all signals containing those candidate connections; (3) rerouting those signals, using a “load-balancing”heuristic; and (4) durin... | 04/26/2005 |
| 6883147 | Method and system for generating a circuit design including a peripheral component connected to a bus Method and system for generating an electronic circuit design. A first logic block is instantiated in the design in response to user input controls. The first logic block includes parameters that specify its interface requirements. Bus interface blocks, which are pa... | 04/19/2005 |
| 6878561 | Mask-alignment detection circuit in X and Y directions Described are mask-alignment detection structures that measure both the direction and extent of misalignment between layers of an integrated circuit using resistive elements for which resistance varies with misalignment in one dimension. Measurements in accordance w... | 04/12/2005 |
| 6879201 | Glitchless pulse generator A glitchless T length pulse is generated by coupling a trigger signal and the latched output of a counter. The trigger signal initiates the start of the T length pulse, and the latched output of the counter initiates the end of the T length pulse after counting up a... | 04/12/2005 |
| 6877040 | Method and apparatus for testing routability A method and apparatus for determining routing feasibility of a plurality of nets. Each net has an associated set of one or more routing solutions, wherein each solution specifies one or more routing resources consumed by the net. A liveness Boolean function is gene... | 04/05/2005 |
| 6873183 | Method and circuit for glitchless clock control A clock control circuit routes one of a plurality of clock signals to a clock output node, and employs an asynchronous state machine to switch between clock signals without introducing glitches. To switch from a first to a second clock, the control circuit samples t... | 03/29/2005 |
