Pizza Pie With Concentric Rings of Crust
A pizza mold for forming a plurality of concentric raised ridges of dough (i.e., crust) on the surface of a pizza pie.
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| Number | Title | Issue Date |
| 7749835 | Trench memory with self-aligned strap formed by self-limiting process A semiconductor structure is described. The structure includes a trench opening formed in a semiconductor substrate having a semiconductor-on-insulator (SOI) layer and a buried insulating (BOX) layer; and a filling material formed in the trench opening, the filling ... | 07/06/2010 |
| 7570174 | Real time alarm classification and method of use A real time alarm classification system and method of use and, more particularly, to a residual gas analyzer configured to identify specific root causes of an abnormal condition such as, for example, contamination, undesirable process variability and equipment malfu... | 08/04/2009 |
| 7569446 | Semiconductor structure and method of manufacture A complimentary metal oxide semiconductor and a method of manufacturing the same using a self-aligning process to form one of the stacks of device. The method includes depositing an oxide layer over a portion of a metal layer over an nFET region of a CMOS structure ... | 08/04/2009 |
| 7557424 | Reversible electric fuse and antifuse structures for semiconductor devices A structure and method of fabricating reversible fuse and antifuse structures for semiconductor devices is provided. In one embodiment, the method includes forming at least one line having a via opening for exposing a portion of a plurality of interconnect features;... | 07/07/2009 |
| 7544608 | Porous and dense hybrid interconnect structure and method of manufacture A method for manufacturing a structure includes depositing a dense dielectric over the entire wafer, which includes areas that require low dielectric capacitance and areas that require high mechanical strength. The method further includes masking areas of the dense ... | 06/09/2009 |
| 7544602 | Method and structure for ultra narrow crack stop for multilevel semiconductor device An integrated circuit design and a method of fabrication and, more particularly, a semiconductor structure having an ultra narrow crack stop for use in multilevel level devices and a method of making the same. The structure includes a first dielectric layer having a... | 06/09/2009 |
| 7543295 | Method for enhancing efficiency in mutual exclusion A system of the present invention includes: a memory device which includes a first memory area for storing first information indicating that a first task acquires or attempts to acquire a lock, and a second memory area for storing second information indicating that ... | 06/02/2009 |
| 7528035 | Vertical trench memory cell with insulating ring A method of forming a vertical transistor trench memory cell having an insulating ring is provided. The method includes forming a semiconductor material region in an etched portion of a semiconductor substrate; partially etching the semiconductor material region to ... | 05/05/2009 |
| 7518145 | Integrated multiple gate dielectric composition and thickness semiconductor chip and method of manufacturing the same A method comprises forming a material over a substrate and patterning the material to remove portions of the material and expose an underlying portion of the substrate. The method further includes performing an oxidation process to form an oxide layer over the expos... | 04/14/2009 |
| 7514339 | Method for fabricating shallow trench isolation structures using diblock copolymer patterning A method of isolating semiconductor devices formed on a semiconductor substrate having a silicon on insulator (SOI) layer is provided. The method includes forming at least one shallow trench area on a pad nitride layer deposited on a surface of the SOI layer, wherei... | 04/07/2009 |
| 7509186 | Method and system for reducing the variation in film thickness on a plurality of semiconductor wafers having multiple deposition paths in a semiconductor manufacturing process A method and system for reducing the variation in film thickness on a plurality of semiconductor wafers having multiple deposition paths in a semiconductor manufacturing process is disclosed. A film of a varying input thickness is applied to semiconductor wafers mov... | 03/24/2009 |
| 7470863 | Microelectronic device with mixed dielectric A microelectronic device and method of making the microelectronic device is provided. A dielectric substrate having first and second surfaces is provided. A first component, located in the dielectric substrate between the first and second surfaces of the dielectric ... | 12/30/2008 |
| 7454723 | Validation of electrical performance of an electronic package prior to fabrication An electrical resistance determination method. Input to the method includes a description of at least one electrical network within a substrate. The description includes specification of a plurality of first ports on a first side of the substrate, and a plurality of... | 11/18/2008 |
| 7442619 | Method of forming substantially L-shaped silicide contact for a semiconductor device A method of manufacturing a semiconductor device having a substantially L-shaped silicide element forming a contact is disclosed. The substantially L-shaped silicide element, inter alia, reduces contact resistance and may allow increased density of CMOS circuits. In... | 10/28/2008 |
| 7406142 | Data recovery circuits using oversampling for best data sample selection An improved data recovery circuit based on an oversampling technique to select the best data sample to be kept as the data to recover that is only based on accumulating the data edges (or transitions). The incoming serial data stream with jitter is oversampled in an... | 07/29/2008 |
| 7377430 | System for secure and accurate electronic voting Performing electronic voting by utilizing the ATM network and ATM machines; issuing voter cards to voters; modifying existing ATM software to recognize the voter card; maintaining a voter registration database; and making the voter registration database available to... | 05/27/2008 |
| 7326651 | Method for forming damascene structure utilizing planarizing material coupled with compressive diffusion barrier material This invention relates to the manufacture of dual damascene interconnect structures in integrated circuit devices. Specifically, a method is disclosed for forming a single or dual damascene structure in a low-k dielectric thin film utilizing a planarizing material a... | 02/05/2008 |
| 7294909 | Electronic package repair process A multilayer ceramic repair process which provides a new electrical repair path to connect top surface vias. The repair path is established between a defective net and a redundant repair net contained within the multilayer ceramic substrate. The defective net and th... | 11/13/2007 |
| 7279426 | Like integrated circuit devices with different depth The invention forms integrated circuit devices of similar structure and dissimilar depth, such as interconnects and inductors, simultaneously. The invention deposits a conformal polymer over an area on a substrate with vias and an area without vias. Simultaneously, ... | 10/09/2007 |
| 7270269 | Secure electronic voting device A secure device for electronic voting employs a write-once vote-recording medium. The medium has an initial writing mode in which data can be written but not read and a subsequent reading mode whereby data can be read but writing is permanently disabled. Once switch... | 09/18/2007 |