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| Number | Title | Issue Date |
| 5208186 | Process for reflow bonding of bumps in IC devices In a semiconductor device tape assembly bonding process the fingers of a copper tape are reflow soldered to metal bumps located on the semiconductor device. First, the semiconductor wafer is covered with a conductive film composed of thin layers of alumin... | 05/04/1993 |
| 5202645 | Stabilized transient response of a cascode CMOS amplifier Operational amplifiers are often used in unity gain configurations where the output is fed back to the input. In the noninverting buffer configuration the output is directly connected to the inverting input and the circuit becomes a voltage follower. In m... | 04/13/1993 |
| 5192712 | Control and moderation of aluminum in silicon using germanium and germanium with boron A process is disclosed for controlling the diffusion of aluminum in silicon for the fabrication of monolithic pn junction isolated integrated circuits. Germanium is incorporated into the silicon where isolation or p-well diffusion of aluminum is to occur.... | 03/09/1993 |
| 5185653 | O-ring package A transfer molded plastic package having a cavity for accommodating a semiconductor chip is disclosed. A leadframe assembly process is shown wherein the leadframe finger pattern is provided with a resilient or elastic O-ring bead. Top and bottom housing p... | 02/09/1993 |
| 5180932 | Current mode multiplexed sample and hold circuit A sample and hold circuit is disclosed in which differentially coupled input stages are multiplexed to drive a common output stage. In this way, a plurality of input stages can be employed wherein the transition between sample and hold modes produces grea... | 01/19/1993 |
| 5157322 | PNP transistor base drive compensation circuit In an integrated circuit a PNP current mirror can lose its current reflection accuracy when low Beta transistors are involved. Since the conventional PNP transistors can often have low Beta this can become a serious problem particularly with high current ... | 10/20/1992 |
| 5151378 | Self-aligned planar monolithic integrated circuit vertical transistor process A process for creating self-aligned vertically arrayed planar transistors. The preferred embodiment relates to the simultaneous fabrication of both NPN and PNP planar vertically arrayed transistors in a conventional monolithic, epitaxial, PN junction isol... | 09/29/1992 |
| 5137838 | Method of fabricating P-buried layers for PNP devices A P-type buried layer is described for use with planar, silicon, monolithic, epitaxial, PN junction-isolated transistors of PNP conductivity primarily for use in IC construction. The buried layer includes a high concentration of boron and gallium along wi... | 08/11/1992 |
| 5136364 | Semiconductor die sealing Integrated circuit bonding pads are sealed by a surface passivation coating. The bonding pads are first edge-sealed by means of a first applied passivation coating that overlaps the edges of the bonding pad while leaving the central area uncoated. Then, a... | 08/04/1992 |
| 5122920 | Low voltage lockout circuit An integrated circuit is shown in which provision is made for terminating or locking out the operating circuitry when the supply voltage has fallen below a level that can cause anomalous or unreliable operation. Certain selected transistors are provided w... | 06/16/1992 |
| 5107189 | RGB video amplifier system integrating blanking and brightness control tracking An RGB video display terminal (VDT) is disclosed and the color cathode ray tube (CRT) driver circuits detailed. The driver circuits include a common video gain control which can be varied over a wide range without changing the DC bias level. Each CRT gun ... | 04/21/1992 |
| 5084633 | Bidirectional current sensing for power MOSFETS A circuit capable of being integrated into a self-isolated DMOST is driven by a sense resistor that is created from the DMOST drain metallization. The circuit produces an output current that is ratioed with respect to the DMOST current with the ratio bein... | 01/28/1992 |
