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Hands free towel carrying system
A hands free towel carrying system for coupling a towel to a user to prevent loss, theft or contamination.
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| Number | Title | Issue Date |
| 5274583 | Charge-integrating preamplifier for ferroelectric memory An integrator circuit is connected to a capacitor that is to be measured and the capacitor driven by a read pulse. A first switch grounds the integrator input between read pulses and a second switch applies a bias input to the integrator. The bias is sele... | 12/28/1993 |
| 5270262 | O-ring package A transfer molded plastic package having a cavity for accommodating a semiconductor chip is disclosed. A leadframe assembly process is shown wherein the leadframe finger pattern is provided with a resilient or elastic O-ring bead. Top and bottom housing p... | 12/14/1993 |
| 5255157 | Plastic pin grid array package with locking pillars A plastic pin grid array package is detailed. Where the semiconductor device is mounted within a cavity in the printed wiring board, it is surrounded by a ring of holes that extend completely through the board. When the plastic housing is transfer molded ... | 10/19/1993 |
| 5236863 | Isolation process for VLSI A process for forming an IC isolation trench pattern wherein the trenches have varying widths and are filled with near intrinsic single crystal silicon. Thus, the wiring that passes over the trenches has low capacitance and active circuit devices having i... | 08/17/1993 |
| 5128272 | Self-aligned planar monolithic integrated circuit vertical transistor process A process for creating self-aligned vertically arrayed planar transistors. The preferred embodiment relates to the simultaneous fabrication of both NPN and PNP planar vertically arrayed transistors in a conventional monolithic, epitaxial, PN junction isol... | 07/07/1992 |
| 4806874 | Switched capacitor amplifier circuit A switched capacitor amplifier circuit using a pair of switched capacitors to replace each resistor element of an inverting operational amplifier circuit, with the capacitors operating on opposite halves of the switching cycle to provide reduced sampling ... | 02/21/1989 |
| 4801561 | Method for making a pre-testable semiconductor die package An encapsulated die package (20) is shown in which a semiconductor die is connected in a die-attach aperture of a copper foil tape (11). Die contact pads (31) are bonded to the inner ends (31a) of interconnected finger contacts (13) on the tape. Finger co... | 01/31/1989 |
| 4798305 | Adjustable shipping tray A shipping tray that can be adjusted to various internal dimensions, by different placement of one or more moveable partitions. The partitions are held in position by means of interlocking surfaces formed on the ends and bottom of the partition and on the... | 01/17/1989 |
| 4778564 | Process for producing an assembly tape for bonding metal fingers to electronic devices In an assembly tape to be used in the tape automated bonding of semiconductor devices a single layer or two or three layer tape is described. The arrays of finger patterns created in the tape are isolated by forming transverse slots across the tape. These... | 10/18/1988 |
| 4775843 | Wideband post amplifier for product detector A wide bandwidth amplifier is coupled to the differential output of a four-quadrant multiplier. The amplifier includes a differential to single-ended input stage driving the inverting input of an operational amplifier which has its noninverting input oper... | 10/04/1988 |
| 4761386 | Method of fabricating conductive non-metallic self-passivating non-corrodable IC bonding pads A monolithic silicon integrated circuit chip is provided with a conductive passivating coating over the metal bonding pads. The coating is composed of doped polysilicon or metal silicide. Such materials provide a self-passivating, non-corrodable surface c... | 08/02/1988 |
| 4758537 | Lateral subsurface zener diode making process A subsurface zener diode is formed in an N type semiconductor substrate such as the kind employed in the epitaxial layer found in silicon monolithic PN junction isolated integrated circuits. A P+ anode is ion implanted into and diffused from an oxide sour... | 07/19/1988 |
| 4757255 | Environmental box for automated wafer probing An automatic wafer probing system is disclosed as being located inside an environmental box filled with a positive pressure dry inert gas. The wafer to be probed is mounted on a Thermochuck that has a high thermal contact with the wafer. The chuck can be ... | 07/12/1988 |
| 4754912 | Controlled collapse thermocompression gang bonding Controlled shape bumps are fabricated into the metal contact fingers that are to be used in the gang bonding assembly of semiconductor devices. The bump shape permits the gang bonding of a plurality of contact fingers simultaneously while producing reliab... | 07/05/1988 |
| 4755767 | High gain amplifier using two current mirrors An op amp is disclosed in which a high-gain differential input stage drives a high-gain common emitter stage that in turn drives an emitter follower buffer output stage. Adequate voltage gain is obtained in only two stages which makes the amplifier easy t... | 07/05/1988 |
| 4743783 | Pulse width modulator circuit for switching regulators A circuit for pulse width modulating the output of a voltage controlled oscillator without introducing any ocillator frequency or amplitude (slope) modulation. A summing circuit is combined with a comparator and provided with inputs that accommodate diffe... | 05/10/1988 |
| 4731696 | Three plate integrated circuit capacitor A capacitor is described having a very low voltage coefficient of capacitance and a relatively large capacitance per unit area. A process is detailed for forming such a capacitor on an IC. The process is fully compatible with conventional IC processing an... | 03/15/1988 |
| 4723197 | Bonding pad interconnection structure Semiconductor devices having bonding pads formed over active regions on the device are fabricated by providing protective layers between the bonding pad and the underlying active region(s). The first protective layer is formed from a polyimide material wh... | 02/02/1988 |
| 4721992 | Hinge tape In an assembly tape to be used in the tape automated bonding of semiconductor devices a single layer or two or three layer tape is described. The arrays of finger patterns created in the tape are isolated by forming transverse slots across the tape. These... | 01/26/1988 |
| 4714517 | Copper cleaning and passivating for tape automated bonding In the preparation of copper parts for the tape automated bonding of semiconductor devices, the copper parts are subjected to a mild organic acid. This treatment etches the copper, removes contaminants and passivates the surfaces so that subsequent oxidat... | 12/22/1987 |
| 4709170 | Subnanosecond programmable phase shifter for a high frequency digital PLL A circuit for producing a programmable phase shift of clock pulses in response to the data on a group of control lines. The circuit includes a ramp generator stage coupled to drive a comparator stage which has a reference potential input determined by the... | 11/24/1987 |
| 4707418 | Nickel plated copper tape An improved copper bump tape for tape automated bonding inhibits electromigration of the copper after bonding to a semiconductor device. The improved tape is characterized by the plating of a migration resistant metal onto the inner ends of connector beam... | 11/17/1987 |
| 4705969 | High accuracy tachometer circuit A tachometer circuit is described that has a zero ripple d-c output that is directly proportional to the frequency. The circuit includes a pair of full wave rectifiers to act upon the sine and cosine signal inputs. The rectified currents are first squared... | 11/10/1987 |
| 4701720 | Capacitive feedback to boost amplifier slew rate An integrated circuit voltage follower buffer amplifier is provided with a feedback capacitor that is coupled to produce positive feedback current that acts to enhance slew rate. In an op amp a polarity sensitive slew rate enhancement acts to correct slew... | 10/20/1987 |
| 4701781 | Pre-testable semiconductor die package An encapsulated die package (20) is shown in which a semiconductor die is connected in a die-attach aperture of a copper foil tape (11). Die contact pads (31) are bonded to the inner ends (31a) of interconnected finger contacts (13) on the tape. Finger co... | 10/20/1987 |
| 4701639 | Threshold detector circuit and method A threshold detector circuit and method for providing an output signal indicative of the relative magnitude of an input signal and a predetermined threshold value. The circuit, which is powered by the input signal and does not require a separate power sou... | 10/20/1987 |
| 4698530 | Power switch for dual power supply circuit A power switching circuit 12 for automatically switching between line-driven and battery power supplies 28 and 30 is disclosed. The power switching circuit selectively connects first and second input voltage terminals Vdd and Vbb to an output voltage term... | 10/06/1987 |
| 4697858 | Active bus backplane A digital bus backplane is disclosed that has interface circuitry located on the backplane. The backplane includes a backplane circuit board containing signal bus lines each operable for conducting electrical signals, several connectors each physically co... | 10/06/1987 |
| 4692688 | Zero standby current switch method and apparatus A bipolar switch is disclosed having a near zero standby current characteristic, low output impedance in the "on" state, and near infinite impedance in the "off" state. The switch is responsive to a control signal to apply regulated power to a load. The s... | 09/08/1987 |
| 4688152 | Molded pin grid array package GPT A pin-grid package is created by starting with printed wiring boards that have plated through holes that can accommodate wire pins. Pins are secured in position to extend outward from one face of the PW board in the form of a pin grid array of the desired... | 08/18/1987 |
| 4684975 | Molded semiconductor package having improved heat dissipation An improved metal tape for tape automated bonding provides for enhanced heat dissipation from the packaged semiconductor device. The invention includes two aspects. In the first aspect, individual metal tape leads are extended inward beyond the peripheral... | 08/04/1987 |
| 4678358 | Glass compression seals using low temperature glass A metal housing is provided with lead in members by way of a compression seal using a glass that can be worked below about 480° C. The housing and lead in members can be preplated in a low cost process to provide a suitable protective coating that is pre... | 07/07/1987 |
| 4672403 | Lateral subsurface zener diode A subsurface zener diode is formed in an N type semiconductor substrate such as the kind employed in the epitaxial layer found in silicon monolithic PN junction isolated integrated circuits. A P+ anode is ion implanted into and diffused from an oxide sour... | 06/09/1987 |
| 4669026 | Power transistor thermal shutdown circuit A thermal shutdown circuit for use with a high power transistor which incorporates a sense emitter. A differential amplifier is driven from the transistor base and the sense emitter and has an output that is coupled to the power transistor base. When the ... | 05/26/1987 |
| 4667265 | Adaptive thermal shutdown circuit An IC thermal shutdown circuit is based upon the thermal characteristics of a reverse biased PN junction diode. The leakage current, at bias levels below breakdown, is closely related to the high temperature IC performance limit. A hysteresis introducing ... | 05/19/1987 |
| 4665328 | Multiple clock power down method and structure A method and structure is provided for powering down a plurality of clocks in a predetermined sequence. In one embodiment, a clock is powered down when it reaches a predefined logical level following the receipt of a power down signal. In another embodime... | 05/12/1987 |
| 4665356 | Integrated circuit trimming A circuit is described for trimming a monolithic PN junction isolated silicon IC. The value of a moderate value resistance network is translated to a current that can be made to have a predetermined temperature coefficient and can be applied to the IC. A ... | 05/12/1987 |
| 4656496 | Power transistor emitter ballasting A power transistor structure that is well suited to both switching and lower-voltage linear applications is displayed. A key element of the design is thin-film ballast resistors that act as a second level of interconnect. They can be connected to or insul... | 04/07/1987 |
| 4656374 | CMOS low-power TTL-compatible input buffer A CMOS buffer is disclosed having a reference potential that provide TTL logic response. The circuit is configured to draw substantially zero current. A reference potential generator develops a potential that is one N channel transistor threshold above ab... | 04/07/1987 |
| 4654826 | Single device transfer static latch Each cell of a static latch implemented in MOS transistor circuitry includes an MOS transistor configured to operate a depletion mode and operably coupled to communicate an output node of the cell to an input node of the cell in absence of a control signa... | 03/31/1987 |
