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| Number | Title | Issue Date |
| 8175717 | Ultracapacitor powered implantable pulse generator with dedicated power supply A stimulator includes an implantable pulse generator comprising circuit elements, a first power source, such as an ultracapacitor, that provides operating power for the circuit elements of the pulse generator. The pulse generator can also have a memory associated th... | 05/08/2012 |
| 8159270 | Circuitry and methods minimizing output switching noise through split-level signaling and bus division enabled by a third power supply Disclosed herein are circuitry and methods for transmitting data across a parallel bus using both high common mode and low common mode signaling. The transmitter stages are configured to work with two of three possible power supply voltages: a high Vddq voltage, a l... | 04/17/2012 |
| 8150713 | Pharmaceutical treatment effectiveness analysis computer system and methods Computer-implemented systems, program code, and related methods are provided. The systems, program code, and methods can be employed to analyze the effectiveness of pharmaceutical treatments for medical conditions utilizing real time prescription compliance records.... | 04/03/2012 |
| 8127424 | Method for assembling components of a microstimulator An electrode assembly includes an electrode electrically connected to a capacitor with a wire. An assembly carrier may be used to hold and secure at least the wire and capacitor during assembly. A method of assembly for attaching a wire to a capacitor and an electro... | 03/06/2012 |
| 8119459 | Recessed channel negative differential resistance-based memory cell Disclosed herein is an improved recessed thyristor-based memory cell. The disclosed cell comprises in one embodiment a conductive plug recessed into the bulk of the substrate, which is coupled to or comprises the enable gate of the cell. Vertically disposed around t... | 02/21/2012 |
| 8094045 | Data bus inversion apparatus, systems, and methods Apparatus, systems, and methods are disclosed such as those that operate to encode data bits transmitted on a plurality of channels according to at least one of multiple Data Bus Inversion (DBI) algorithms. Additional apparatus, systems, and methods are disclosed. | 01/10/2012 |
| 7573733 | Self-identifying stacked die semiconductor components A semiconductor die having a functional circuit (e.g., a memory array) and a decode circuit suitable for use in a stacked die semiconductor component (e.g., a random access memory component) is described. The decode circuit permits individual die in a stacked die st... | 08/11/2009 |
| 7535282 | Dynamic well bias controlled by Vt detector The p- well back bias for NCH transistors in a DRAM sense amplifier circuit is dynamically adjusted. Preferably, during sensing, the p- well back bias for the NCH transistors of the sense amp is increased to in effect lower the threshold voltages for the NCH transis... | 05/19/2009 |
| 7492287 | Two-bit tri-level forced transition encoding An encoding technique is disclosed for mitigating against the effects of Intersymbol Interference (ISI) and DC creep by forcing data transitions at least every two data bits. Two consecutive bits of data in the original non-return-to-zero (NRZ) data stream are group... | 02/17/2009 |
| 7470882 | Reduction in size of column sample and hold circuitry in a CMOS imager Improved column sample-and-hold (CSH) circuitry particularly useful in a CMOS imager is disclosed. In the improved circuitry layout, the overall column height of the CSH circuitry is reduced by providing a plurality of pairs of sampling and reference capacitors in a... | 12/30/2008 |
| 7443216 | Trimmable delay locked loop circuitry with improved initialization characteristics Disclosed herein is improved delay locked loop (DLL) initialization circuitry that alters the measurement used to initialize the variable delay line's delay (e.g., entry point or exit point) by using three clock phases: the DLL reference clock (input to the delay li... | 10/28/2008 |
