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| Number | Title | Issue Date |
| 6372570 | Method of formation of a capacitor on an integrated circuit A method of manufacturing a capacitor includes the steps of depositing a first metal level and etching it to leave in place a region corresponding to a first plate of a capacitor and an area of contact with an upper level; depositing an insulating layer; ... | 04/16/2002 |
| 6332136 | Fuzzy filtering method and associated fuzzy filter The fuzzy filtering of a noise signal comprising a plurality of signal samples [s(t,k)] is carried out using as variables the variation of the signal in the considered window and the distance of the samples from a sample to be reconstructed, to distinguis... | 12/18/2001 |
| 6326271 | Asymmetric MOS technology power device A MOS technology power device comprises a semiconductor substrate, a semiconductor layer of a first conductivity type superimposed over the semiconductor substrate, an insulated gate layer covering the semiconductor layer, a plurality of substantially rec... | 12/04/2001 |
| 6314043 | Erasing and parallel rewriting circuit for memory cell blocks, particularly for analog flash cells, and related operating method Circuit for erasing and rewriting blocks of memory cells and particularly of analog flash cells, including at least one row decoding circuit including at least two adder blocks, suitable to generate a row address signal, at least two decoder blocks, suita... | 11/06/2001 |
| 6314041 | Memory with a reduced leakage current A SRAM including an array of memory cell lines and columns, each column being supplied between a high supply voltage and a low supply voltage, which includes at least one MOS transistor in series with each column, and circuitry for applying to the at leas... | 11/06/2001 |
| 6313040 | Process for the definition of openings in a dielectric layer A process for etching a dielectric layer, including the steps of forming, over the dielectric layer, a layer of polysilicon, forming over the layer of polysilicon a photoresist mask layer, etching the layer of polysilicon using the photoresist mask layer ... | 11/06/2001 |
| 6304126 | Protection circuit that can be associated with a filter A structure for protection against electrostatic surges having two input terminals and two output terminals. The output terminals of the structure are connected to the inputs of a circuit to be protected. A first input terminal is connected to a first out... | 10/16/2001 |
| 6301657 | System and method for booting a computer There is disclosed a computer,system including a microprocessor on an integrated circuit chip comprising an on-chip CPU and a communication bus. The communication bus provides a parallel communication path between the CPU and the first memory local to the... | 10/09/2001 |
| 6300171 | Method of manufacturing an integrated edge structure for high voltage semiconductor devices, and related integrated edge structure Method of manufacturing an edge structure for a high voltage semiconductor device, including a first step of forming a first semiconductor layer of a first conductivity type, a second step of forming a first mask over the top surface of the first semicond... | 10/09/2001 |
| 6297093 | Method of making an electrically programmable memory cell The present invention relates to a method of manufacturing an electrically programmable memory cell with a lateral floating gate with respect to the control gate, including the steps of forming an insulated control gate on an active area; forming a thin i... | 10/02/2001 |
| 6295580 | Cache system for concurrent processes A method of operating a cache memory is described in a system in which a processor is capable of executing a plurality of processes, each process including a sequence of instructions. In the method a cache memory is divided into cache partitions, each cac... | 09/25/2001 |
| 6294901 | Power dimmer The present invention relates to a power dimmer of a load, powered by an a.c. voltage, of the type including a bidirectional switch associated in series with the load, the switch being normally closed and controllable to be opened upon each halfwave of th... | 09/25/2001 |
| 6294443 | Method of epitaxy on a silicon substrate comprising areas heavily doped with boron A method of vapor phase epitaxy deposition of silicon on a silicon substrate on or in which exist areas containing dopants at high concentration, among which is boron, while avoiding a selfdoping of the epitaxial layer by boron, including the step of intr... | 09/25/2001 |
| 6292347 | Electric arc generation circuit A circuit of electric arc generation from an A.C. voltage, includes circuitry for making the electric arc frequency substantially independent from possible amplitude variations of the A.C. voltage.... | 09/18/2001 |
| 6289069 | Digital filter for rotation correction loop of a QPSK or QAM demodulator The present invention relates to a digital filter for a phase-locked loop receiving at least one input signal having a predetermined period, including an element of accumulation of frequency values receiving the output of a phase detector; and an element ... | 09/11/2001 |
| 6288658 | Antisaturation system for an analog-to-digital converter A digital signal processing system, including an analog-to-digital converter adapted to provide at least n-bit samples to a processor, and range selection circuitry for stepwise adjusting the range of the analog-to-digital converter to the amplitude of an... | 09/11/2001 |
| 6282125 | Method for erasing and rewriting non volatile memory cells and particularly flash cells A method for erasing non volatile memories, in particular flash cells, that includes applying erasing pulses to the cells to be erased and to verify, after each pulse, the value of the threshold voltage of the cells. The erasing pulses are provided to the... | 08/28/2001 |
| 6281723 | Device and method for power-on/power-off checking of an integrated circuit A checking device to control the power-on or power-off operations in an integrated circuit comprises a voltage reference circuit biased by a bias circuit, and an output stage. The device further comprises a control circuit to activate or deactivate the bi... | 08/28/2001 |
| 6281722 | Bias source control circuit The invention relates to a control circuit for a bias source including a stand-by device and a starting-aid device, with their respective outputs connected to a control input of the bias source, the starting-aid device including a switch to inhibit its op... | 08/28/2001 |
| 6281566 | Plastic package for electronic devices A semiconductor electronic device comprises a chip of a semiconductor material, a set of metal conductors adjacent to the plate, a set of wire leads joining selected points on the chip to the metal conductors, and a supporting metal plate formed of three ... | 08/28/2001 |
| 6281157 | Self-catalytic bath and method for the deposition of a nickel-phosphorus alloy on a substrate Disclosed are a self-catalytic bath and a method for the deposition of Ni--P alloy on a substrate. The bath comprises nickel sulfate, sodium hypophosphite as a reducing agent, acetic acid as a buffer and traces of lead as a stabilizer. It also includes a ... | 08/28/2001 |
| 6279103 | Method and device for providing an instruction trace from an on-chip CPU using control signals from the CPU There is disclosed a single chip integrated circuit device comprising an instruction trace controller operable to monitor an address in memory of instructions to be executed by an on-chip CPU. The instruction trace controller is connected to trace storage... | 08/21/2001 |
| 6279068 | Set of two memories on the same monolithic integrated circuit Two different types of memory are integrated on the same type of integrated circuit. A microcontroller is associated with each of these memories. In order that the independence of operation of these microcontrollers may be ensured, they are each provided ... | 08/21/2001 |
| 6278868 | Transceiver circuit including a circuit for measuring the delay introduced by telephone lines The present invention relates to a master transceiver circuit meant to be coupled by a telephone line to a slave transceiver circuit, the master circuit including a digital phase-locked loop for reconstructing a clock from an incoming bit flow, the phase ... | 08/21/2001 |
| 6268747 | Dynamic voltage sense amplifier A sense amplifier includes a bistable circuit and a control circuit. The bistable circuit has first and second input/output terminals connected to two input lines via a gating circuit. The bistable circuit has positive and negative supply nodes, one of wh... | 07/31/2001 |
| 6265277 | Method for making a bipolar transistor for the protection of an integrated circuit against electrostatic discharges In a method for the making of a lateral bipolar transistor, the formation of a field oxide layer on the surface of the substrate, between the collector and the emitter of the protection transistor, is avoided. The lateral bipolar transistors made by the d... | 07/24/2001 |
| 6263324 | Method and apparatus for the use of a fuzzy logic processor in a network A fuzzy logic processor placed in a home automation communications network manages messages traveling through the network. To manage the messages, the fuzzy logic processor works in two stages. In a first stage, on a first part of the message, the fuzzy l... | 07/17/2001 |
| 6262443 | Monolithic protected rectifying bridge The present invention relates to a semiconducting structure constituting a protected rectifying bridge implemented in an N-type semiconductor substrate divided into first, second, and third wells by vertical P-type isolating walls, in which the rear surfa... | 07/17/2001 |
| 6259626 | Method for storing bytes in multi-level non-volatile memory cells A method for storing n bytes in multi-level non-volatile memory cells, including writing and reading of said n bytes. Writing includes the following steps: (a) decomposing each one of such n bytes into eight bits, (b) storing each one of such eight bits i... | 07/10/2001 |
| 6259022 | Chip card micromodule as a surface-mount device A micromodule is used as a surface-mounted package on a substrate of interconnections. In one embodiment of the invention, barriers to the expansion of solder are formed between contact zones of the micromodule and corresponding contact pads of the substr... | 07/10/2001 |
| 6259018 | Conductor structure A wiring structure has at least three conductors each having a respective first portion running substantially mutually parallel on the first planar path and a second portion, the second portions running substantially mutually parallel on a second planar p... | 07/10/2001 |
| 6258720 | Method of formation of conductive lines on integrated circuits The present invention relates to a method of formation of a conductive line on integrated circuits including the steps of etching a first insulator layer to create therein openings of predetermined width at the locations where the conductive line is to be... | 07/10/2001 |
| 6253352 | Circuit for validating simulation models A circuit for measuring a propagation time of an edge of a signal between an input and an output of a logic cell. The circuit includes a plurality of logic cells of a first type that are electrically coupled in a series, and a plurality of multiplexers, e... | 06/26/2001 |
| 6252451 | Switching circuit A one-way switching circuit of the type including a gate tun-off thyristor biased to be normally on, further includes, between the gate and a supply line, a capacitor and a controllable switch connected in parallel.... | 06/26/2001 |
| 6252449 | Clock distribution circuit in an integrated circuit The present invention relates to an integrated circuit including at least one logic circuit, able to operate at a first operating frequency, and a clock distribution circuit, the clock distribution circuit receiving a first clock signal and providing to t... | 06/26/2001 |
| 6252442 | Electronic circuit provided with a neutralization device A neutralization device is provided that is designed to block the operation of an electronic circuit when this device is insufficiently supplied. The device is designed especially for electronic circuits supplied with low supply voltages. The neutralizati... | 06/26/2001 |
| 6252257 | Isolating wall between power components The present invention relates to an isolating wall for separating elementary components formed in different wells, a component located in at least one of the wells being capable of operating with a high current density. The isolating wall exhibits in its ... | 06/26/2001 |
| 6249409 | Protection of a vertical MOS transistor associated with measurement cells The present invention relates to a device of protection of a monolithic component including a MOS-type vertical diffused power transistor formed of a great number of identical cells, and a measurement transistor formed of a smaller number of cells identic... | 06/19/2001 |
| 6249172 | Circuit for discharging a negative potential node to ground, including control of the discharge current Circuit for discharging to ground, supplied by a supply voltage, comprising a reference voltage, a negative potential node, first circuitry adapted to couple the negative potential node to the reference voltage in response to a control signal. Second circ... | 06/19/2001 |
| 6248630 | Process for forming an integrated circuit comprising non-volatile memory cells and side transistors and corresponding IC A process for forming an integrated circuit includes at least one matrix of non-volatile memory cells having an intermediate dielectric multilayer including at least a lower dielectric material layer and an upper silicon oxide layer. The integrated circui... | 06/19/2001 |
