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| Number | Title | Issue Date |
| 6433382 | Split-gate vertically oriented EEPROM device and process A split-gate EEPROM transistor includes a channel region (22) formed in a vertically disposed semiconductor body (58) and residing intermediate to a drain region (26) and a source region (24). A select gate electrode (28) is horizontally disposed on a sem... | 08/13/2002 |
| 6238967 | Method of forming embedded DRAM structure A method for forming an embedded DRAM integrated circuit (10) begins by forming an asymmetric source and drain structure on the DRAM pass transistors. The asymmetric DRAM transistor structure has a lightly doped shallow current electrode (60) that connect... | 05/29/2001 |
| 6150190 | Method of formation of buried mirror semiconductive device A method for forming a buried optical mirror in an integrated circuit (IC) begins by forming an opening (18) within a substrate (12). The opening (18) is then filled with a plurality of dielectric layers (20-26) that have different indexes of refraction w... | 11/21/2000 |
| 6146970 | Capped shallow trench isolation and method of formation A method for forming a capped shallow trench isolation (CaSTI) structure begin by etching a trench opening (210). The opening (210) is filled with an oxide or like trench fill material (216b) via a deposition and chemical mechanical polish (CMP) step. The... | 11/14/2000 |
| 6146948 | Method for manufacturing a thin oxide for use in semiconductor integrated circuits A method for forming a gate dielectric having different thickness begins by providing a substrate (12). A sacrificial oxide (14) is formed overlying the substrate (12). A first portion (11) of the sacrificial oxide (14) is exposed to a carbon-containing p... | 11/14/2000 |
| 6045435 | Low selectivity chemical mechanical polishing (CMP) process for use on integrated circuit metal interconnects A method for polishing a metal layer (20) containing a combination of wide features (12), low density features (14), and high density features (18), is illustrated. A hydrophilic polish pad (24) having a shore D hardness of greater than 50 is used along w... | 04/04/2000 |
| 6037202 | Method for growing an epitaxial layer of material using a high temperature initial growth phase and a low temperature bulk growth phase A method for forming a trench transistor structure begins by forming a buried layers (12 and 16) and a doped well (22) in a substrate (10) via epitaxial growth processing. A trench region (24) is then etched into the substrate (10) to expose a the layer (... | 03/14/2000 |
| 6028003 | Method of forming an interconnect structure with a graded composition using a nitrided target A method for forming an interconnect structure on a semiconductor wafer (114) begins by placing the wafer (114) in a process chamber (100). The process chamber (100) contains a titanium (Ti) target (102) having a thin titanium nitride (TiN) layer (104) fo... | 02/22/2000 |
| 6020024 | Method for forming high dielectric constant metal oxides A method for forming a metal gate (20) structure begins by providing a semiconductor substrate (12). The semiconductor substrate (12) is cleaned to reduce trap sites. A nitrided layer (14) having a thickness of less than approximately 20 Angstroms is form... | 02/01/2000 |
| 6011719 | Digital signal processor having an on-chip pipelined EEPROM data memory and a on-chip pipelined EEPROM program memory A nonvolatile memory architecture (10) contains a plurality of memory arrays (12) formed by a plurality of floating gate memory cells and supports a 1× and 2× architecture. The nonvolatile memory design contains high voltage row decoders (16), low volta... | 01/04/2000 |
| 6010927 | Method for making a ferroelectric device having a tantalum nitride barrier layer A method for forming CMOS transistors and ferroelectric capacitors on a single substrate (10) with improved yield begins by forming CMOS transistors (37a, 37b, 40, 42). A hydrogen anneal using 4-5% hydrogen and a remainder nitrogen is performed to reduce ... | 01/04/2000 |
| 6004850 | Tantalum oxide anti-reflective coating (ARC) integrated with a metallic transistor gate electrode and method of formation A method for forming a tantalum-based anti-reflective coating (ARC) layer begins by forming an MOS metallic gate electrode layer (20) over a substrate (20). The MOS metallic gate electrode layer (20) is covered with an ARC layer (22). The ARC layer is pre... | 12/21/1999 |
| 6001730 | Chemical mechanical polishing (CMP) slurry for polishing copper interconnects which use tantalum-based barrier layers A method for forming a copper interconnect on an integrated circuit (IC) begins by forming a dielectric layer (20) having an opening. A tantalum-based barrier layer (21), such as TaN or TaSiN, is formed within the opening in the layer (20). A copper layer... | 12/14/1999 |
| 6001726 | Method for using a conductive tungsten nitride etch stop layer to form conductive interconnects and tungsten nitride contact structure A method for forming a contact structure (10) which enables the use of ultra-shallow source/drain junctions begins by forming source and drain regions (14) and gate electrode (16). The source and drain regions (14) and the gate electrode (16) are silicide... | 12/14/1999 |
| 5982166 | Method for measuring a characteristic of a semiconductor wafer using cylindrical control The time required to make test measurements across a large diameter wafer, such as a 300 mm wafer, is reduced by using a wafer measuring system that employs theta (θ) and radial (r) control instead of X-Y control. In one embodiment, a measurement arm (14... | 11/09/1999 |
| 5977632 | Flip chip bump structure and method of making A passivation layer (16) is formed over a substrate (10) having an interconnect pad (12, 13). An opening in the passivation layer (16) exposes a portion of the interconnect pad (12, 13). A polyimide structure (18, 20) is formed adjacent to the opening in ... | 11/02/1999 |
| 5964863 | Method and apparatus for providing pipe fullness information external to a data processing system The present invention relates in general to a data processing system (10), and more particularly to a method and apparatus for providing instruction pipe (106) status information, including fullness information, external to data processing system (10). In... | 10/12/1999 |
| 5963315 | Method and apparatus for processing a semiconductor wafer on a robotic track having access to in situ wafer backside particle detection The present disclosure is a method for in situ monitoring of backside contamination on a semiconductor wafer (120) between processing steps which are performed in a multi-chamber tool (500). In a first form, a laser source (220) and a detector (210) are m... | 10/05/1999 |
| 5963818 | Combined trench isolation and inlaid process for integrated circuit formation A method for forming an integrated circuit involves forming trench isolation regions (208a) and a damascene gate electrode region (214) simultaneous with one another via overlapping process steps. By performing this simultaneous formation of a trench regi... | 10/05/1999 |
| 5959462 | Test structure for enabling burn-in testing on an entire semiconductor wafer A test structure and test methodology are taught herein wherein a test structure (10) is used to test an entire integrated circuit product wafer (44). The test structure (10) has a backing support wafer (39). A die attach compound (38) is used to attach a... | 09/28/1999 |
| 5960270 | Method for forming an MOS transistor having a metallic gate electrode that is formed after the formation of self-aligned source and drain regions A method for forming a metal gate MOS transistor begins by forming source and drain electrodes (26, 28, and/or 118) within a substrate (12 or 102). These source and drain regions (26, 28, and 118) are self-aligned to a lithographically-patterned feature (... | 09/28/1999 |
| 5960289 | Method for making a dual-thickness gate oxide layer using a nitride/oxide composite region A method for forming a dual gate oxide (DGO) structure begins by forming a first oxide layer (106) within active areas (110) and (112). A protection layer (108a) is then formed over the layer (106). A mask (114) is used to allow removal of the layers (106... | 09/28/1999 |
| 5949706 | Static random access memory cell having a thin film transistor (TFT) pass gate connection to a bit line A memory circuit and method of formation uses a transmission gate (24) as a select gate. The transmission gate (24) contains a transistor (30) which is an N-channel transistor and a transistor (28) which is a P-channel transistor. The transistors (28 and ... | 09/07/1999 |
| 5945354 | Method for reducing particles deposited onto a semiconductor wafer during plasma processing A method for reducing particles (235) during a semiconductor process. A semiconductor substrate (230) is placed into a processing chamber (210). A processing pressure (108) is applied within the chamber (212). A processing power (102) is applied to the ch... | 08/31/1999 |
| 5930586 | Method and apparatus for in-line measuring backside wafer-level contamination of a semiconductor wafer A method and apparatus for detecting copper (Cu) contamination on the backside of a wafer (120) begins by providing the wafer (120). The wafer (120) is rotated about a rotational axis via a motor/computer controlled wafer stage (118). In addition to rotat... | 07/27/1999 |
| 5910680 | Germanium silicate spin on glass semiconductor device and methods of spin on glass synthesis and use A semiconductor device (11) has a spin on glass layer or region, and the spin on glass has a method of synthesis and use. The spin on glass composition is formed which comprises on the order of 0% to 20% by volume of tetraethylorthosilicate (TEOS), on the... | 06/08/1999 |
| 5910994 | Method and apparatus for suppressing acoustic feedback in an audio system A method (FIGS. 6-8) for detecting and attenuating N feedback frequencies in a digitized signal uses a tree structure containing a plurality of staged filters. In a step (602), an array of digital filters (FIG. 8) having N branches (40) is constructed. Th... | 06/08/1999 |
| 5907865 | Method and data processing system for dynamically accessing both big-endian and little-endian storage schemes A method and apparatus is used to allow big-endian data and little-endian data to be read from memory in a dynamic manner. A multiplexer controller (18) is provided size bits and two low order address bits A0 and A1 as control signals from a CPU (16). A0 ... | 05/25/1999 |
| 5903919 | Method and apparatus for selecting a register bank Method and apparatus for selecting one of a plurality of banks of registers in a register file of a data processor. The register specifier fields of an instruction are logically combined with respective register bank specifier fields of a control register... | 05/11/1999 |
| 5898619 | Memory cell having a plural transistor transmission gate and method of formation A memory circuit and method of formation uses a transmission gate (24) as a select gate. The transmission gate (24) contains a transistor (30) which is an N-channel transistor and a transistor (28) which is a P-channel transistor. The transistors (28 and ... | 04/27/1999 |
| 5897375 | Chemical mechanical polishing (CMP) slurry for copper and method of use in integrated circuit manufacture A method for chemical mechanical polishing (CMP) a copper layer (22) begins by forming the copper layer (22). The copper layer (22) is then exposed to a slurry (24). The slurry (24) contains an oxidizing agent such as H2 O2, a carbox... | 04/27/1999 |
| 5892682 | Method and apparatus for generating a hierarchical interconnection description of an integrated circuit design and using the description to edit the integrated circuit design Data processing system (800) and process (100) produce a hierarchical interconnection description of an integrated circuit design from a plurality of functional modules and a desired hierarchy. After an integrated circuit description is received (102), an... | 04/06/1999 |
| 5889788 | Wrapper cell architecture for path delay testing of embedded core microprocessors and method of operation An integrated circuit contains customer specified logic (12), an embedded core (14), and a plurality of speed path test cells (16 and 18). Once the core (14) is embedded within an integrated circuit (10), not all of the input and output terminals of the e... | 03/30/1999 |
| 5889999 | Method and apparatus for sequencing computer instruction execution in a data processing system A method and apparatus for sequencing computer instructions in memory (24) to provide for more instruction efficient execution by a central processing unit (CPU) (22) begins by executing the computer instructions via the CPU (22) and creating a trace file... | 03/30/1999 |
| 5889303 | Split-Control gate electrically erasable programmable read only memory (EEPROM) cell An EEPROM cell (32) is formed having a vertical select gate (34) and a horizontal select gate (40). The vertical select gate (34) and the horizontal select gate (40) enable two dimensional decoding which selects which one or which plurality of memory cell... | 03/30/1999 |
| 5885856 | Integrated circuit having a dummy structure and method of making A pattern of dummy structures (20) is added to the layout pattern of an integrated circuit (10) to equilibrate the polishing rate across the surface of a semiconductor substrate (11). The location of each dummy structure (20) is predetermined so that it d... | 03/23/1999 |
| 5886382 | Trench transistor structure comprising at least two vertical transistors A method for forming a trench transistor structure begins by forming a buried layers (12 and 16) and a doped well (22) in a substrate (10) via epitaxial growth processing. A trench region (24) is then etched into the substrate (10) to expose a the layer (... | 03/23/1999 |
| 5883907 | Asymmetrical digital subscriber line (ADSL) block encoder circuit and method of operation A method and apparatus for performing block encoding in an asymmetrical digital subscriber line (ADSL) system uses a pipelined structure. The parity check circuit (116) contains a plurality of pipeline stages (201, 203, 205, and 207). Each stage contains ... | 03/16/1999 |
| 5879971 | Trench random access memory cell and method of formation A method for forming a random access memory cell within four separate trench regions (106, 108, 110, and 112). One half of the memory cell has a first N-type transistor, which is a latch transistor (500), has a current electrode (101), a current electrode... | 03/09/1999 |
| 5867405 | Ferroelectric simulator, ferroelectric method of manufacture, and method of simulation A method and apparatus for simulating the design of a ferroelectric circuit uses a processor (501). The processor (501) executes a simulator (540) from memory (538) to exercise a ferroelectric model (544). The ferroelectric model (544) keeps track of turn... | 02/02/1999 |
