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| Number | Title | Issue Date |
| 7231986 | Well tool protection system and method The system including a well tool having a housing forming a protection fluid chamber in fluid communication with a discharge port, a protection fluid disposed within the protection fluid chamber, and a moveable mechanism in functional connection with the protection ... | 06/19/2007 |
| 7194195 | Software based digital video recorder device A system and method for converting information stored on a magnetic medium to DVD format. A tape transport mechanism may sample information stored on a magnetic medium at a selected rate where the selected rate is correlated to an available buffer size in a data pro... | 03/20/2007 |
| 7169229 | Moving head, coating apparatus The invention pertains to a coating apparatus and method in which most of the relative movement between a dispensing head and the substrate to be coated is provided by the coating head. The moving head configuration reduces the system footprint and diminishes leveli... | 01/30/2007 |
| 7164681 | Mechanism to strip LARQ header and preserve LARQ header in status frame The present invention provides a method for supporting frame priority in a home phone line network. The method includes: detecting a limited automatic repeat request (LARQ) header in a frame with a priority tag; stripping the LARQ header and a frame check sequence (... | 01/16/2007 |
| 7160389 | System and method for cleaning and priming an extrusion head The present invention relates to a system and method suitable for automatic cleaning of a coating or extrusion head of a coating apparatus. The invention includes a scrubbing station wherein a combination of physical contact and strong solvent solution combine to re... | 01/09/2007 |
| 7139213 | Multiple data path memories and systems The invention describes and provides multiple data path memories and systems utilizing such memories. Enhanced data throughput and bandwidth, while substantially simultaneously providing improved bus utilization, are some of the benefits. In peer-to-peer connected s... | 11/21/2006 |
| 7107487 | Fault tolerant sleep mode of operation A method, system and computer program product for implementing a fault tolerant sleep mode of operation. The system state information may be stored in a volatile memory and in a non-volatile storage unit prior to entering the sleep mode of operation. If a memory cor... | 09/12/2006 |
| 7093479 | Method and apparatus for indicating a parameter of transmitted fluid The invention concerns a method and apparatus for indicating a parameter of a transmitted fluid. One embodiment of the invention comprises a fluid source operatively coupled to a conduit for transmitting a fluid from the fluid source. In addition, a sensor detects a... | 08/22/2006 |
| D526220 | Phosphor reader | 08/08/2006 |
| D520987 | Remote control | 05/16/2006 |
| 7047382 | System and method for managing compression and decompression and decompression of system memory in a computer system A method and system for allowing a processor or I/O master to address more system memory than physically exists are described. A Compressed Memory Management Unit (CMMU) may keep least recently used pages compressed, and most recently and/or frequently used pages un... | 05/16/2006 |
| 6986876 | Method for forming composites of sub-arrays of single-wall carbon nanotubes This invention relates generally to forming arrays of single-wall carbon nanotubes (SWNT). In one embodiment, the present invention involves forming a macroscopic molecular array of tubular carbon molecules, said method comprising the step of assembling subarrays of... | 01/17/2006 |
| 6936233 | Method for purification of as-produced single-wall carbon nanotubes This invention relates generally to a single-wall carbon nanotube (SWNT) purification process and more particularly to a purification process that comprises heating the SWNT-containing felt under oxidizing conditions to remove the amorphous carbon deposits and other... | 08/30/2005 |
| 6896911 | Process for the production of oryzanol enriched fraction from rice bran oil soapstock The present invention relates to an improved process for the production of oryzanol enriched fraction from rice bran oil soapstock; the present invention particularly relates to saponification, dehydration and leaching of rice bran oil soapstock for production of or... | 05/24/2005 |
| 6859965 | Tension relieving apparatus for arms and neck A tension relieving apparatus for the arms and neck which combines a generally oblong shaped pillow with first and second ends having attached connecting members which are further attached to first and second resiliently tensioned arm supporting members. The interio... | 03/01/2005 |
| 6697812 | Method and system for eliminating error when packing or packaging sets of serialized products or otherwise identifiable products A method of preparing a set of items for future business processes includes the step of grouping the items to be included in the set, each of the items associated with a unique identifier. The unique identifiers are then recorded en masse and communicated... | 02/24/2004 |
| 6695207 | System for secure, identity authenticated, and immediate financial transactions as well as activation of varied instrumentalities The present invention concerns apparatus and methods for a family of electronic devices based on the concept of a Personalized Authenticated Controller (PAC). The PAC is able to recognize characteristics of an authorized person and allows only that person... | 02/24/2004 |
| 6628999 | Single-chip audio system volume control circuitry and methods An audio system 100 includes circuitry 116 for generating an audio data stream and circuitry 103 for generating digital words defining a volume control level. System 100 also includes volume control circuitry 5000 for controlling the amplitude of the audi... | 09/30/2003 |
| 6622208 | System and methods using a system-on-a-chip with soft cache A soft cache system compares tag bits of a virtual address with tag fields of a plurality of soft cache register entries, each entry associated with an index to a corresponding cache line in virtual memory. A cache line size for the cache line is programm... | 09/16/2003 |
| 6601622 | Personal accessory with quick-access A personal accessory includes an outer cover and a pocket disposed within the body and accessible through an aperture through the outer cover. A holder includes a peripheral frame defining at least one window for receiving and holding a substantially flat... | 08/05/2003 |
| 6603415 | Circuits and methods for latch metastability detection and compensation and systems using the same Metastable compensation circuitry 700 for detecting and compensating for metastable states of a regenerative latch 209 in a charge redistribution analog to digital converter 201. First and second latches 701a,b each having a selected threshold voltage for... | 08/05/2003 |
| 6587066 | Circuits and methods for sampling an input signal in a charge redistribution digital to analog converter A method and a circuit of performing an analog to digital conversion in a charge redistribution circuit including a capacitor array of weighted capacitors and a transistor track switch for sampling an input signal into the capacitor array. A common mode v... | 07/01/2003 |
| 6584546 | Highly efficient design of storage array for use in first and second cache spaces and memory subsystems A method of operating a cache memory includes the step of storing a set of data in a first space in a cache memory, a set of data associated with a set of tags. A subset of the set of data is stored in a second space in the cache memory, the subset of the... | 06/24/2003 |
| 6577287 | Dual variable color display device A single variable color display device simultaneously exhibits two distinct display units in a side by side relation. Two color controls are provided for illuminating the display units in respectively different colors so they could be readily distinguishe... | 06/10/2003 |
| 6574728 | Condition code stack architecture systems and methods A computer system includes a register file and an arithmetic logic unit (ALU) for reading data from the register file. The ALU is configured to conduct data processing of the data which was and to store the results of the data processing in the register f... | 06/03/2003 |
| 6574668 | Retransmission scheme in wireless computer networks Data is transmitted over a computer network from a source network component to one or more destination network components. Thereafter, one or more acknowledgements are transmitted from one of the destination network components to the source network compon... | 06/03/2003 |
| 6552979 | Optical servo control circuits and methods using pulse width modulation and offset control for driving an electromechanical motor Servo control circuitry 300 includes a digital to analog converter 402 for converting digital servo control data into a pulse width modulated signal. A first conductor transmits the pulse width modulated signal to an external device 409. A second conducto... | 04/22/2003 |
| 6549652 | Method and apparatus for reducing noise during lossy transformation processes Processing digital information made up of a plurality of n-bit samples is performed by raising each n-bit value to an x-bit value, x being greater than n. The x-bit values represent mid-band values, wherein in this context a band includes a sequential set... | 04/15/2003 |
| 6538594 | Methods and circuits for compensating for finite common mode rejection in switched capacitor circuits A method of compensating for finite common mode rejection in a switched capacitor circuit including arrays of input capacitors coupled to first and second differential nodes, includes the step of sampling a common mode voltage onto the differential nodes ... | 03/25/2003 |
| 6535018 | Voltage level shifting circuits and methods and systems using the same A level shifter 200 for shifting a logic high voltage of an input signal from a lower voltage to a higher voltage includes a latch 204 for storing a bit of data and having an output for driving a stored logic high bit at the higher voltage. A data node is... | 03/18/2003 |
| 6535186 | Multicolor display element A multicolor display element includes a plurality of display areas arranged in a pattern. Each display area includes three light emitting diodes for emitting light signals of respectively different colors. The light emitting diodes of the same color are c... | 03/18/2003 |
| 6525589 | Application of a conditionally stable instrumentation amplifier to industrial measurement An instrumentation circuit has an integrated circuit that has input terminals, an amplifier arrangement using feed forward compensation and an analog to digital converter and a serial data output receiving the output from said amplifier arrangement. A bri... | 02/25/2003 |
| 6522273 | Circuits systems and methods for power digital-to-analog converter protection An apparatus and method for power digital-to-analog converter protection are implemented. An attenuation value is set in response to the value of the supply voltage. The attenuation value is provided to a gain control, along with the input signal. A gain,... | 02/18/2003 |
| 6515540 | High order multi-path operational amplifier with output saturation recovery An amplifier is disclosed including multiple integrator stages. The amplifier includes a low-frequency path from a signal input to a signal output and relatively higher-frequency bypass paths around the first integrator stage. The paths converge at a summ... | 02/04/2003 |
| 6513130 | Circuits, systems, and methods for accounting for defective cells in a memory device A data processing system 100 is provided which includes a memory 104, an array 204 of memory cells arranged in rows and columns, each row being addressable by an address. Address generation circuitry 201/202 is provided for generating ones of the addresse... | 01/28/2003 |
| 6512705 | Method and apparatus for standby power reduction in semiconductor devices A word line driver circuit for a semiconductor memory device. One or more transistors in the driver circuit are fabricated such that they are susceptible, under certain conditions, to gate-induced diode leakage (GIDL). One terminal of the transistors are ... | 01/28/2003 |
| 6510098 | Method and apparatus for transferring data in a dual port memory A memory system 20 includes a first array 100 and a second array 102 of memory cells. The memory system allows for a quick transfer of the contents of one of the arrays with another one of the arrays. Through the use of a transfer gate (128) interposed be... | 01/21/2003 |
| 6509790 | Switched-capacitor circuits and methods with improved settling time and systems using the same A switched capacitor circuit (300) including an operational amplifier (206) having an input and an output, a sampling capacitor (203) and a set of switches (204, 205, 301, and 302) are disclosed. During a first phase, switches (201, 204) sample an input v... | 01/21/2003 |
| 6504786 | High speed, scalable, dynamic integrated programmable switch (DIPS) device An asymmetrical switching element including a random access memory element, a first port selectively coupled to the memory element by first control signal and a plurality of second ports, each independently coupled to the memory element by corresponding o... | 01/07/2003 |
| 6504785 | Multiprocessor system with integrated memory A multiprocessor processing 200 includes a memory system having a memory controller 202 for linking a plurality of processors 201 with an integrated memory 203. Integrated memory 203 comprises a plurality of static random access arrays 603 and a dynamic r... | 01/07/2003 |
