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| Number | Title | Issue Date |
| 6040218 | Two square NVRAM cell A non-volatile random access memory (NVRAM) cell and method of fabrication thereof. Pairs of NVRAM cells, each including three FETs stacked in a NAND-like structure are formed vertically in silicon pillars. Source devices at the bottom of the pillar selec... | 03/21/2000 |
| 6040954 | High speed write driver for magnetic inductive write head using a half-switched H-driver A write driver in an H configuration for magnetic inductive write heads characterized by having both arms in the bottom half of the driver conduct current all the time, with only the top devices being switched. In this configuration there is no need to sy... | 03/21/2000 |
| 6026019 | Two square NVRAM cell A non-volatile random access memory (NVRAM) cell and method of fabrication thereof. Pairs of NVRAM cells, each including three FETs stacked in a NAND-like structure are formed vertically in silicon pillars. Source devices at the bottom of the pillar selec... | 02/15/2000 |
| 6022770 | NVRAM utilizing high voltage TFT device and method for making the same Breakdown and latch-up of field effect transistors integrated with non-volatile semiconductor memory cells requiring voltages higher than logic level voltages for write and erase operations is avoided while limiting process complexity and constraints and ... | 02/08/2000 |
| 6015993 | Semiconductor diode with depleted polysilicon gate structure and method A high voltage tolerant diode structure for mixed-voltage, and mixed signal and analog/digital applications. The preferred silicon diode includes a polysilicon gate structure on at least one dielectric film layer on a semiconductor (silicon) layer or body... | 01/18/2000 |
| 6013936 | Double silicon-on-insulator device and method therefor An integrated circuit chip wherein one or more semiconductor devices are completely isolated from bulk effects of other semiconductor devices in the same circuit and a method of making the integrated circuit chip. The devices may be passive devices such a... | 01/11/2000 |
| 6003059 | Carry select adder using two level selectors A carry select adder including a two level carry selector connected to multiple carry chains. Two or more adders produce at least two pairs of candidate carry-out signals in parallel. For each pair, a first candidate carry-out signal is based on a first p... | 12/14/1999 |
| 5923097 | Switching supply test mode for analog cores An integrated circuit such as an application specific integrated circuit (ASIC) which has operational power supplies provided for different respective analog cores and digital logic and/or macros may be tested using on-chip power supplies, preferably comp... | 07/13/1999 |
| 5923574 | Optimized, combined leading zeros counter and shifter By combining a count leading zero circuit with a bit shifter in a digital processor though detection of groups of leading zeros prior to completion of counting of leading zeros, shifting for normalization and number format conversion can concurrently be i... | 07/13/1999 |
| 5883566 | Noise-isolated buried resistor A noise-isolated buried resistor satisfies the requirements for low-noise analog designs requiring well controlled ohmic resistors. A field shield is provided between the buried resistor and the substrate to isolate the buried resistor from the substrate ... | 03/16/1999 |
| 5793592 | Dynamic dielectric protection circuit for a receiver A topology for arranging a plurality of transistors between a signal source and an off-chip receiver, using a single power supply voltage. A pass through NFET has a gate controlled by a network comprised of two transistors arrayed between the power supply... | 08/11/1998 |
| 5789966 | Distributed multiplexer Signal propagation time through a transmission gate array or multiplexer is significantly reduced and output signal transition time is halved by detecting non-selection of a section of the multiplexer and activating an output circuit, preferably in the fo... | 08/04/1998 |
| 5776660 | Fabrication method for high-capacitance storage node structures A high capacitance storage node structure is created in a substrate by patterning a hybrid resist (12) to produce both negative tone (16) and positive tone (18) areas in the exposed region (14). After removal of the positive tone areas (18), the substrate... | 07/07/1998 |
