Quotables
"Everyone acquainted with the subject will recognize it as a conspicuous failure."
Henry Morton, president of the Stevens Institute of Technology ; Said in 1880 about the light bulb
PatentStorm News
Make the Most of Our Site
See this month's Top Inventors and Most Cited Patents.
Stay on top of the latest innovations by subscribing to an RSS feed.
Registered users: Manage your profile.
| Number | Title | Issue Date |
| 5666506 | Apparatus to dynamically control the out-of-order execution of load/store instructions in a processor capable of dispatchng, issuing and executing multiple instructions in a single processor cycle An apparatus to dynamically controls the out-of-order execution of load/store instructions by detecting a store violation condition and avoiding the penalty of a pipeline recovery process. The apparatus permits a load and store instruction to issue and ex... | 09/09/1997 |
| 5644744 | Superscaler instruction pipeline having boundary identification logic for variable length instructions A mechanism which manages variable length instructions in cache is comprised of three cooperating elements designed to optimize self modifying code and anticipate next instructions for branch operand management. A content addressable memory (CAM) stores a... | 07/01/1997 |
| 5644536 | High gain feedback latch A latch circuit includes a plurality of transistors, a set input for receiving a set signal coupled to a first transistor of the plurality of transistors, a reset input for receiving a reset signal coupled to a second transistor of the plurality of transi... | 07/01/1997 |
| 5640526 | Superscaler instruction pipeline having boundary indentification logic for variable length instructions A mechanism which manages variable length instructions in cache is comprised of three cooperating elements designed to optimize self modifying code and anticipate next instructions for branch operand management. A content addressable memory (CAM) stores a... | 06/17/1997 |
| 5636157 | Modular 64-bit integer adder A high speed, compact low power integer adder unit for advanced microprocessors features modular construction, low gate count and a fast add time. A 64-bit implementation is characterized by a unique combination of dual rail logic circuits and dual carry ... | 06/03/1997 |
| 5629901 | Multi write port register A multi-write port register is provided with a local clock buffer (LCB) to control a gate on the input port to reduce potential timing hazards. The LCB provides flexible logic function and is controlled by a clock and word-line inputs. In addition, the LC... | 05/13/1997 |
| 5625787 | Superscalar instruction pipeline using alignment logic responsive to boundary identification logic for aligning and appending variable length instructions to instructions stored in cache A mechanism which manages variable length instructions in cache is comprised of three cooperating elements designed to optimize self modifying code and anticipate next instructions for branch operand management. A content addressable memory (CAM) stores a... | 04/29/1997 |
| 5605277 | Hot vacuum device removal process and apparatus A cost efficient, highly reliable method to remove electronic devices and components from substrates eliminates separate tooling for every substrate and device or component size. The apparatus which implements the method allows for multiple device or comp... | 02/25/1997 |
| 5592674 | Automatic verification of external interrupts A method for the automatic verification of external interrupts in modern processor architectures under a very wide range of instruction sequences provides almost complete expected results from each of the involved interrupts. In particular, the method all... | 01/07/1997 |
| 5541881 | High gain feedback latch A latch circuit includes a plurality of transistors, a set input for receiving a set signal coupled to a first transistor of the plurality of transistors, a reset input for receiving a reset signal coupled to a second transistor of the plurality of transi... | 07/30/1996 |
