Bizarre Patents
Behavior Modification Wristwatch
A wristwatch including a watch band and a watch body having an octagon shaped perimeter and being red in color and having the word STOP thereon to resemble a stop sign.
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| Number | Title | Issue Date |
| 5694564 | Data processing system a method for performing register renaming having back-up capability In a data processing system, a method for performing register renaming with back-up capability. A register renaming apparatus (18) comprises a logical-physical (LP) register map (30), a free list (32), and an internal swap bus (90) for exchanging informat... | 12/02/1997 |
| 5513358 | Method and apparatus for power-up state initialization in a data processing system A method and apparatus for implementing a power-up state initialization. A power sense circuit provides a signal for indicating when the power supply, VDD, is of a voltage level greater than the minimum voltage level suitable for safely resolvi... | 04/30/1996 |
| 5511100 | Method and apparatus for performing frequency detection A method and apparatus for performing frequency detection in an all digital phase lock loop (10). Frequency detection is accomplished using a frequency detector (11), coupled to an digitally controlled oscillator (DCO 16). The frequency detector (11) forc... | 04/23/1996 |
| 5506875 | Method and apparatus for performing frequency acquisition in all digital phase lock loop A method and apparatus for performing frequency acquisition. Frequency acquisition is accomplished by utilizing binary-search techniques with a controller (13), variable digital oscillator (16), frequency detector (11) an incrementor (19) and decrementor ... | 04/09/1996 |
| 5506971 | Method and apparatus for performing a snoop-retry protocol in a data processing system A data processing system (10) and method for performing a snoop-retry protocol using an arbiter (14). Multiple bus masters (12, 16, 17) are coupled to multiple shared buses (20, 22, 24, 26). Each bus master (12, 16, 17) may initiate a bus transaction ("in... | 04/09/1996 |
| 5473285 | Method and apparatus for performing phase acquisition in an all digital phase lock loop A method and apparatus for performing, after frequency acquisition, phase acquisition and phase maintenance in a digital phase-locked loop 10. A phase detector (12), determines the phase relation of an oscillator output to a reference clock signal, and pr... | 12/05/1995 |
| 5420543 | Method and apparatus for determining a constant gain of a variable oscillator A method and apparatus for implementing a constant gain in a digitally-controlled variable oscillator (DCO) 16 where the frequency of the DCO 16 is controlled via binary-weighted control signals. The frequency of the DCO 16 is modulated via arithmetic inc... | 05/30/1995 |
| 5416910 | Method and apparatus for performing bus arbitration in a data processing system A data processing system (10) and method for performing bus arbitration protocol using an arbiter (14). The data processing system (10) has multiple bus masters (12, 16) each of which is coupled to multiple shared buses (20, 22, 24, 28). The arbiter (14) ... | 05/16/1995 |
| 5410669 | Data processor having a cache memory capable of being used as a linear ram bank A data processing system (10) having a dual purpose memory (14) comprising multiple cache sets. Each cache set can be individually configured as either a cache set or as a static random access memory (SRAM) bank. Based upon the configuration of the set, t... | 04/25/1995 |
| 5381116 | Method and apparatus for performing frequency tracking in an all digital phase lock loop An all digital phase lock loop (ADPLL), (10) includes a variable digital oscillator (DCO 16), a phase detector (12), a controller (13) including an incrementor (19) and decrementor (21), and a set of oscillator control registers (22). A frequency tracking... | 01/10/1995 |
| 5373461 | Data processor a method and apparatus for performing postnormalization in a floating-point execution unit A method and apparatus for performing prenormalization during execution by an execution unit (100) of a floating-point add/subtract operation using two data operands. The execution unit (100) adds a mantissa portion of a first and a second floating-point ... | 12/13/1994 |
| 5357237 | In a data processor a method and apparatus for performing a floating-point comparison operation A data processor (10) has a floating-point execution unit (32) for executing a floating-point compare operation using two data operands. The execution unit (32) uses mantissa comparator logic (107) to perform a bit-wise comparison of a mantissa portion of... | 10/18/1994 |
| 5355457 | Data processor for performing simultaneous instruction retirement and backtracking A data processing system is provided which has more general purpose physical registers than architectural (logical) registers. The data processing system uses a register inventory system to monitor the allocation state changes of each of the physical regi... | 10/11/1994 |
| 5317701 | Method for refilling instruction queue by reading predetermined number of instruction words comprising one or more instructions and determining the actual number of instruction words used A sequential prefetch method is provided for a pipelined data processor having a sequential instruction prefetch unit (IPU). An instruction queue in the IPU is coupled to a pipelined instruction unit and an instruction cache of the data processor. A prefe... | 05/31/1994 |
| 5287523 | Method for servicing a peripheral interrupt request in a microcontroller A method for servicing peripheral interrupt requests in a data processing system is provided. A state vector register stores a current state of a state machine which controls the interrupt-generating peripheral. In addition, the state vector register simu... | 02/15/1994 |
| 5276635 | Method and apparatus for performing carry look-ahead addition in a data processor A carry look-ahead (CLA) adder accommodates a late carry-in from a low-order external 32-bit adder to enable a 96-bit addition to be performed in the same time in which the CLA adder (60) performs a 64-bit addition. Within each adder slice, intermediate g... | 01/04/1994 |
| 5272660 | Method and apparatus for performing integer and floating point division using a single SRT divider in a data processor A method and apparatus for performing integer and floating-point divide operations using a single modified SRT divider in a data processor. The floating-point and integer division is performed using SRT division on normalized positive mantissas (dividend ... | 12/21/1993 |
| 5268995 | Method for executing graphics Z-compare and pixel merge instructions in a data processor A method for performing graphics Z-compare and pixel merge operations, for use in a Z-buffering system to remove hidden surfaces when displaying a three-dimensional image, is provided. The data processing system includes a main memory for storing data and... | 12/07/1993 |
| 5265043 | Wallace tree multiplier array having an improved layout topology A Wallace tree multiplier array (40) performs multiply operations using operands received via a data path (42) having a predetermined height. Rows of carry save adders (CSAs 15'-19") add sets of partial products to generate sets of intermediate summands, ... | 11/23/1993 |
| 5249280 | Microcomputer having a memory bank switching apparatus for accessing a selected memory bank in an external memory A memory expansion scheme is provided which permits a program to automatically cross memory bank boundaries, without user intervention. A memory bank address register stores a value corresponding to a selected memory bank (i.e. Bank 0), in a 4-bit subfiel... | 09/28/1993 |
| 5199032 | Microcontroller having an EPROM with a low voltage program inhibit circuit A microcontroller is provided having an on-chip electrically erasable programmable read-only-memory (EEPROM), which is user programmable via a programming register. The microcontroller includes a low voltage program inhibit (LVPI) circuit which is combine... | 03/30/1993 |
| 5197144 | Data processor for reloading deferred pushes in a copy-back data cache A data processor is provided for reloading deferred pushes in copy-back cache. When a cache "miss" occurs, a cache controller selects a cache line for replacement, and request a burst line read to transfer the required cache line from an external memory. ... | 03/23/1993 |
| 5185694 | Data processing system utilizes block move instruction for burst transferring blocks of data entries where width of data blocks varies A block MOVE instruction allows a programmer to issue an instruction to a loosely coupled system bus controller, thereby facilitating the execution of a memory to memory move of multiple data entries, utilizing a burst mode transfer onto the system bus fo... | 02/09/1993 |
| 5173617 | Digital phase lock clock generator without local oscillator A digital phase lock loop that does not depend on a voltage controlled oscillator (VCO) for phase locking. A phase detector (PD), terminated with a latch, controls an up/down counter that programs an increase/decrease of delay on the delay line. The tappe... | 12/22/1992 |
| 5170476 | Data processor having a deferred cache load A data processing system is provided having a secondary cache for performing a deferred cache load. The data processing system has a pipelined integer unit which uses an instruction prefetch unit (IPU) to maintain a steady stream of instructions to the pi... | 12/08/1992 |
| 5155825 | Page address translation cache replacement algorithm with improved testability A replacement method is provided for improving the hit rate and testability of a page address translation cache (PATC). The replacement scheme uses a modified FIFO replacement algorithm. A circular shift register has a pointer which points to each of a pr... | 10/13/1992 |
| 5155824 | System for transferring selected data words between main memory and cache with multiple data words and multiple dirty bits for each address A data cache capable of operation in a write-back (copyback) mode. The data cache design provides a mechanism for making the data cache coherent with memory, without writing the entire cache entry to memory, thereby reducing bus utilization. Each data cac... | 10/13/1992 |
| 5101344 | Data processor having split level control store A data processor having a split level control store structure, which partitions program memory into a macrocode portion and a microcode portion. The data processor contains two distinct machines, a macromachine and a micromachine. The macromachine include... | 03/31/1992 |
| 5053949 | No-chip debug peripheral which uses externally provided instructions to control a core processing unit A data processing system having a debug peripheral is provided. The debug peripheral is coupled to a central processing unit and memory via an internal communications bus. The debug peripheral is a single-word dual port memory with parallel read-write wri... | 10/01/1991 |
| 5041742 | Structured scan path circuit for incorporating domino logic A design for a structured scan path circuit incorporating domino logic circuitry is provided. The scan path circuit allows the rapid evaluation of a predetermined logic function, while allowing the use of automatic test pattern generation programs. Each f... | 08/20/1991 |
| 5015875 | Toggle-free scan flip-flop A toggle-free scan flip-flop (TFSFF) is provided which is designed for use during a test mode scan operation. The toggle-free scan flip-flop has the capability of not toggling its parallel output during test mode scan operation. The TFSFF uses a master la... | 05/14/1991 |
| 4982363 | Sensing structure for single ended input A single-ended sense amplifier, for fast sensing from a precharged low condition, is provided. In the precharge mode, the amplifier discharges the sensing node to ground, and charges a bias node to a first predetermined voltage. This bias node modulates t... | 01/01/1991 |
| 4977541 | EPROM programming An EPROM memory transistor programming arrangement is disclosed in which programming voltage for a memory transistor is applied via a load line of series connected N-channel MOS transistors which are controlled by low voltage NAND gate having low voltage ... | 12/11/1990 |
| 4959561 | MOS output buffer with reduced supply line disturbance An output buffer with reduced supply line disturbance is provided for use in high performance microprocessor circuits. The output buffer uses a resistor and transistor as a sensing circuit, in parallel with an output driver transistor, thereby providing a... | 09/25/1990 |
