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| Number | Title | Issue Date |
| 8185720 | Processor block ASIC core for embedding in an integrated circuit A hardwired core is embedded in an integrated circuit having programmable circuitry. The hardwired core has a microprocessor; a crossbar interconnect coupled to processor local buses of the microprocessor; and a memory controller interface coupled to the crossbar in... | 05/22/2012 |
| 8184029 | Phase interpolator A phase interpolator is described. The phase interpolator can have a code-to-bias converter, and a phase interpolation interface. In an embodiment of a code-to-bias converter, a single digital-to-analog converter is provided to generate bias signaling associated wit... | 05/22/2012 |
| 8183881 | Configuration memory as buffer memory for an integrated circuit Method and apparatus for using configuration memory for buffer memory is described. Drivers associated with a portion of the configuration memory are rendered incapable of creating a contentious state irrespective of information stored the portion of configuration m... | 05/22/2012 |
| 8166366 | Partial configuration of programmable circuitry with validation Partial configuration of programmable circuitry with validation for an integrated circuit is described. An integrated circuit with programmable circuitry is obtained. The programmable circuitry is configured with a first bitstream in a non-dynamic mode of operation,... | 04/24/2012 |
| 8161365 | Cyclic redundancy check generator A cyclic redundancy check (“CRC”) generator and method therefor are described. Checksum bits and checksum enable bits are bitwise ANDed to provide interim checksum outputs. The interim checksum outputs are XORed to provide resultant checksum outputs. Data bits a... | 04/17/2012 |
| 8146045 | High-level circuit architecture optimizer A method for optimizing a high-level circuit architecture for an integrated circuit is described. Descriptions of components of the circuit architecture and optimization goals for the components are received. At least one stopping criterion for the cost functions is... | 03/27/2012 |
| 8145877 | Address generation for quadratic permutation polynomial interleaving For address generation, a block size and a skip value are obtained, and at least one address, at least one increment value, and a step value are initialized. For a count index not in excess of a block size, iteratively performed are: selection of an output address f... | 03/27/2012 |
| 8136075 | Multilevel shared database for routing A multilevel shared database for routing for an integrated circuit is described. An aspect relates generally to a database comprising routing edges defined by tile templates. The routing edges are associated with a plurality of wire length segmentations. The tile te... | 03/13/2012 |
| 8136073 | Circuit design fitting Circuit design fitting for an integrated circuit is described. A mapped design for the circuit design is obtained. A first placement of the mapped design in association with an integrated circuit is performed. Circuit blocks are marked associated with the integrated... | 03/13/2012 |
| 8134418 | Varactor circuit and voltage-controlled oscillation A varactor circuit and voltage-controlled oscillation are described. The varactor circuit includes a first varactor, a second varactor, a third varactor, and a fourth varactor. A first source-drain node of the first varactor and a second source-drain node of the sec... | 03/13/2012 |
| 8131788 | Determining sum of absolute differences in parallel Determining a sum of absolute differences using a circuit is described. Pairs of inputs, including a respective current value and a respective previous value, are obtained. The previous value is subtracted from the current value for each of the pairs of inputs to pr... | 03/06/2012 |
| 8116372 | Data structure and method using same for encoding video information A data structure and method of use thereof for encoding video information are described. Macroblock parameters are initialized, and it is determined whether an operating point is selected. If the operating point is selected, then the following occurs: each quad of n... | 02/14/2012 |
| 8099625 | Self-checking and self-correcting internal configuration port circuitry Method and apparatus for self-checking and self-correcting memory states of a programmable resource is described. Programmable resource of an integrated circuit has a first core and a second core instantiated therein. A first internal configuration port and a second... | 01/17/2012 |
| 8090755 | Phase accumulation A method for accumulation of information is described. The information is separated into first portions of MSBs and second portions of LSBs. The first and second portions are respectively input to a first adder and a second adder to provide first and second sums. Th... | 01/03/2012 |
| 8090037 | OFDM modulation using a shaping filter Reducing peak-to-average power ratio (“PAPR”) for modulation and demodulation is described. Complex sample values are obtained in a time domain for orthogonal frequency division multiplexed (“OFDM”) signaling. The complex sample values are transformed into a... | 01/03/2012 |
| 8077776 | Motion estimation for video compression Motion estimation is described. A first portion of a predicted frame is obtained. The first portion is for a first predicted value. A first subset of a reference frame is obtained. The first subset is for a first reference value. Twice the first predicted value is s... | 12/13/2011 |
| 8068004 | Embedded inductor An embedded inductor and a method for forming an inductor are described. Spaced apart first stripes are formed substantially parallel with respect to one another as part of a first metal layer. First contacts, second contacts, and third contacts in respective combin... | 11/29/2011 |
| 8042079 | Synchronization for a modeling system Design synchronization for a High-Level Modeling System (“HLMS”) of an integrated circuit device (“IC”) is described. In a method for generating a netlist, a description of a first circuit block of a user design is input to a programmed computer system progr... | 10/18/2011 |
| 8024688 | Deterring reverse engineering A method for detecting reverse engineering of a configuration bitstream for an integrated circuit is described. A user design is obtained. It is determined if the user design is a degenerate design. If the user design is a degenerate design, it is determined if a tr... | 09/20/2011 |
| 8019950 | Memory controller interface for an embedded processor block core in an integrated circuit A method for address acknowledgement is described. A memory controller interface is embedded as part of an embedded core in a host integrated circuit. Access to the memory controller interface is arbitrated with an arbiter. An accept signal is sent from the memory c... | 09/13/2011 |
| 8018250 | Input/output block and operation thereof An embodiment of a method for operation of an input/output block is disclosed. For this embodiment of the method, a first attribute is set for a first disable signal for an input driver. A first tri-state condition is removed from an output driver. In response to th... | 09/13/2011 |
| 8006068 | Processor access to data cache with fixed or low variable latency via instructions to an auxiliary processing unit Access to data storage is described. A general-purpose processor and an auxiliary processing unit (APU) interface coupled to the general-purpose processor are provided. Data storage coupled to the general-purpose processor via the APU interface is provided for a fix... | 08/23/2011 |
| 8006021 | Processor local bus bridge for an embedded processor block core in an integrated circuit A processor local bus bridge for a processor block ASIC core for embedding in an IC is described. A core logic-to-core logic bridge includes a slave processor local bus interface, a crossbar switch coupled to the slave processor local bus interface and a master proc... | 08/23/2011 |
| 8005881 | Scalable architecture for rank order filtering A rank order filter and instantiation thereof in programmable logic is described. A maximum filter core frequency is determined for an input sampling frequency, a filter window height, and a number of input samples. The maximum filter core frequency is greater than ... | 08/23/2011 |
| 8001171 | Pipeline FFT architecture for a programmable device A pipeline Fast Fourier Transform (“FFT”) architecture for a programmable device is described. A first Radix-2 butterfly stage is coupled to receive a first input, configured to provide a first output responsive thereto, and configured to truncate at least one L... | 08/16/2011 |
| 7992020 | Power management with packaged multi-die integrated circuit Power management with a packaged multi-die integrated circuit (IC) is described. A first integrated circuit die is capable of a first operational mode. A second integrated circuit die is coupled to the first integrated circuit die. The first integrated circuit die h... | 08/02/2011 |
| 7991937 | Network media access controller embedded in a programmable device—receive-side client interface A receive-side client interface for a media access controller embedded in an integrated circuit having programmable circuitry is described. A media access controller core includes a receive engine. A receive-side datapath is coupled to the media access controller co... | 08/02/2011 |
| 7984407 | Programmable device with contact via programming A programmable device with contact via programming to reduce leakage current and a method for reducing standby power for such programmable device are described. Configuration memory cells are identified responsive to instantiation of a user design in a test platform... | 07/19/2011 |
| 7984091 | Quadratic approximation for fast fourier transformation Interpolators for quadratic approximation for sinusoids are described. A sample source providing first order derivatives of sub-sampled sets of phase factor samples is used. A differentiator is coupled to receive the first order derivatives and configured to provide... | 07/19/2011 |
| 7979831 | Placement driven control set resynthesis Circuit placement for increasing circuit packing density for an integrated circuit is described. A design is synthesized and mapped. Components of the design are placed to provide a first placed design. A congestion density map is generated for the first placed desi... | 07/12/2011 |
| 7969187 | Hardware interface in an integrated circuit A hardware interface in an integrated circuit is disclosed. The hardware interface comprises data storage coupled to store and provide data; a data shifter coupled to the data storage to at least bit shift the data obtained from the data storage; and a control circu... | 06/28/2011 |
| 7965801 | Digital data recovery Data recovery, as well as associated circuitry and system, is described. An input word stream having a word width of at least one word is obtained and a sliding window is applied to it to resolve phases. Scores for phases are determined at least in part by: subdivid... | 06/21/2011 |
| 7965799 | Block boundary detection for a wireless communication system Method and apparatus for block boundary detection is described. A signal is received. The signal is quantized to provide a quantized signal to at least one correlator, the quantized signal being a sequence of samples. The sequence of samples and a reference template... | 06/21/2011 |
| 7965102 | Formation of columnar application specific circuitry using a columnar programmable device A columnar programmable device (PD) design converted to a columnar application specific integrated circuit-like (ASIC-like) design is described. A user design is instantiated in a PD having a columnar architecture associated with the columnar PD design. The columnar... | 06/21/2011 |
| 7958414 | Enhancing security of internal memory An embodiment of a method of enhancing security of internal memory is disclosed. For this embodiment of the method, the application specific block is operated in a functional mode, and a reset of the application specific block is initiated. From a built-in self-test... | 06/07/2011 |
| 7934038 | Embedded network media access controller A media access system in an integrated circuit device having programmable resources for interfacing to a network. The media access system has at least one embedded media access controller configured to provide access to and from the network via a physical layer inte... | 04/26/2011 |
| 7919845 | Formation of a hybrid integrated circuit device Formation of a hybrid integrated circuit device is described. A design for the integrated circuit is obtained and separated into at least two portions responsive to component sizes. A first die is formed for a first portion of the hybrid integrated circuit device us... | 04/05/2011 |
| 7917820 | Testing an embedded core A method of testing of an embedded core of an integrated circuit (“IC”) is described. An IC has a hardwired embedded core and memory coupled to each other in the IC. The method includes writing a test vector to the memory while the embedded core is operative. Th... | 03/29/2011 |
| 7917567 | Floating-point processing unit for successive floating-point operations A floating-point processing unit for a succession of floating-point operations. An exponent adjustor is coupled to receive numerical inputs and configured to generate first adjusted values from the numerical inputs. The first adjusted values have equivalent exponent... | 03/29/2011 |
| 7912997 | Direct memory access engine A direct memory access engine is described. The direct memory access engine has a transmit channel coupled to a transmit interface, a receive channel coupled to a receive interface, an arbiter coupled to both the transmit channel and the receive channel, and a set o... | 03/22/2011 |
