Did You Know...
...that power steering was invented by independent inventor Francis W. Davis? As chief engineer in the 1920s of the truck division of the Pierce Arrow Motor Car Company, he saw how hard it was to steer heavy vehicles. So that he would be able to keep the profits from his future invention, Davis left his job, rented a small engineering shop in Waltham, Mass., and developed a hydraulic power steering system that led to power steering.
PatentStorm News
Make the Most of Our Site
See this month's Top Inventors and Most Cited Patents.
Stay on top of the latest innovations by subscribing to an RSS feed.
Registered users: Manage your profile.
| Number | Title | Issue Date |
| 7981731 | Method of forming a high impedance antifuse A programmable element that has a first diode having an electrode and a first insulator disposed between the substrate and said electrode of said first device, said first insulator having a first value of a given characteristic, and an FET having an electrode and a ... | 07/19/2011 |
| 7914949 | Method for testing a photomask A method, a recording medium and an apparatus for testing a photomask are provided. In the disclosed method, a particular region of a photomask is selected, either from a physical instance of the photomask, or from the photomask as represented by a digital represent... | 03/29/2011 |
| 7456671 | Hierarchical scalable high resolution digital programmable delay circuit A hierarchical and modular clock programmable delay circuit structure is described that can achieve almost unlimited fine resolution and unlimited delay range. The same circuit may also be applied to critical circuits that require fine adjustment in timing applicati... | 11/25/2008 |
| 7194670 | Command multiplier for built-in-self-test Disclosed is a flexible command multiplication scheme for the built-in-self test (BIST) of a high-speed embedded memory array that segments BIST functionality into remote lower-speed executable instructions and local higher-speed executable instructions. A stand-alo... | 03/20/2007 |
| 7191305 | Method and apparatus for address decoding of embedded DRAM devices A method for decoding a memory array address for an embedded DRAM (eDRAM) device is disclosed, the eDRAM device being configured for operation with an SDRAM memory manager. In an exemplary embodiment of the invention, the method includes receiving a set of row addre... | 03/13/2007 |
| 7139944 | Method and system for determining minimum post production test time required on an integrated circuit device to achieve optimum reliability A method and system for determining minimum post production test time on an integrated circuit device to achieve optimal reliability of that device utilizing defect counts. The number of defective cells or active elements with defective cells (DEFECTS) on the integr... | 11/21/2006 |
| 7138326 | Wafer integrated rigid support ring A shadow mask for depositing solder bumps includes additional dummy holes located adjacent holes corresponding to most of the perimeter chips of the wafer. The additional dummy provide more uniform plasma etching of contacts of the wafer, improve etching of contacts... | 11/21/2006 |
| 7098083 | High impedance antifuse A programmable element that has a first diode having an electrode and a first insulator disposed between the substrate and said electrode of said first device, said first insulator having a first value of a given characteristic, and an FET having an electrode and a ... | 08/29/2006 |
| 7064570 | Method for locating Idefects using multiple controlled collapse chip connections current measurement on an automatic tester A method for improving the signal-to-noise ratio in an IDDQ defect test is disclosed. An integrated circuit is divided into a plurality of areas and each area is provided with and bounded by terminals. An IDDQ defect is activated to generate I | 06/20/2006 |
| 7016251 | Method and apparatus for initializing SRAM device during power-up A method for initializing a static random access memory (SRAM) device during power-up includes clamping one of a pair of bitlines of the SRAM device to a logic low potential while allowing the other of the pair of bitlines to be coupled to a charging logic high pote... | 03/21/2006 |
| 7012826 | Bitline twisting structure for memory arrays incorporating reference wordlines A bitline structure for a memory array includes a first pair of complementary bitlines and a second pair of complementary bitlines. Both the first and second pair of complementary bitlines have a twist at a location corresponding to about ΒΌ of the total length of t... | 03/14/2006 |
| 7013441 | Method for modeling integrated circuit yield A method and system for predicting manufacturing yield for a proposed integrated circuit The method includes: in the order recited: (a) providing a multiplicity of different integrated circuit library elements in a design database, each library element linked to a c... | 03/14/2006 |
| 7010733 | Parametric testing for high pin count ASIC A method for reducing Pin Count Test design and test that allows parametric test patterns for high pin count ASICs to be applied using low pin count testers. The same boundary scan structure used to isolate the test of internal logic to a small number of test I/O is... | 03/07/2006 |
| 7007214 | Diagnosable scan chain A method and system for locating connector defects in a defective scan chain that has a parallel non-defective scan chain on a different wiring level, with both scan chains being laid out in a regular array pattern. A predetermined bit sequence is scanned into the d... | 02/28/2006 |
| 6998866 | Circuit and method for monitoring defects A circuit and a method for monitoring defects in an integrated circuit chip. The circuit including a defect monitor portion and a sense element portion, the defect monitor portion either coupled to inputs of sense elements arranged in a chain or coupled between sens... | 02/14/2006 |
| 6995585 | System and method for implementing self-timed decoded data paths in integrated circuits A self-timed data transmission system includes a data bit group defined by at least two data bits to be transmitted from a corresponding plurality of transmitting storage elements. A corresponding plurality of data receiving storage elements receives the data transm... | 02/07/2006 |
| 6996791 | Method for optimizing a set of scan diagnostic patterns A method and system for generating a set of scan diagnostic patterns for diagnosing fails in scan chains. The method including: (a) selecting a set of latches; (b) selecting a pattern from a set of test patterns; (c) determining the number of lateral insertions of t... | 02/07/2006 |
| 6993692 | Method, system and apparatus for aggregating failures across multiple memories and applying a common defect repair solution to all of the multiple memories An integrated circuit includes a plurality of separate memory arrays each having a respective one of a plurality of inputs and a respective one of a plurality of outputs. Each output provides an output value indicative of whether a storage location associated with a... | 01/31/2006 |
| 6989685 | Method and system for maintaining uniform module junction temperature during burn-in A method for controlling the burn-in temperature of a semiconductor chip includes determining a DC current of the chip, and determining a difference between the DC current and a target current, the target current being selected to produce a desired chip temperature.... | 01/24/2006 |
| 6967557 | Wafer test space transformer A space transformer including a body; a ground conductor within the body; a power conductor within the body, the power conductor adapted to be at a higher voltage level than a voltage level of the ground conductor; and one or more decoupling capacitors physically lo... | 11/22/2005 |
| 6967861 | Method and apparatus for improving cycle time in a quad data rate SRAM device A method for implementing a self-timed, read to write operation in a memory storage device. In an exemplary embodiment, the method includes capturing a read address during a first half of a current clock cycle, and commencing a read operation so as to read data corr... | 11/22/2005 |
| 6967556 | High power space transformer A space transformer for use in an integrated circuit wafer test system, the space transformer including: a ground conductor; a power conductor; and one or more decoupling capacitors physically located between the ground conductor and the power conductor and electric... | 11/22/2005 |
| 6961886 | Diagnostic method for structural scan chain designs A method for testing and diagnosing shift register latch chains coupled to logic circuits in an integrated circuit, the method including: (a) determining which of the shift register latch chains are failing by propagating a test pattern of zeros and ones through the... | 11/01/2005 |
| 6954389 | Dynamic semiconductor storage device and method of reading and writing operations thereof To provide a dynamic semiconductor storage device featuring reduced power consumption and faster operation of a sense amplifier. The drain of a transistor N7 constituting an N-type sense amplifier NSAt is connected to a shared line SA, while the drain of a tr... | 10/11/2005 |
| 6944090 | Method and circuit for precise timing of signals in an embedded DRAM array A method and circuit for timing the start of a precharge period in an eDRAM. The circuit including: a delayed lock loop circuit for receiving a clock signal and generating a control signal for adjusting an internal delay of the clock signal; and means for generating... | 09/13/2005 |
| 6931346 | Method and apparatus for reduced pin count package connection verification A method and apparatus for testing the chip-to-package connectivity of a common I/O of a semiconductor chip is disclosed which uses reduced pin count testing methods. The method includes driving a test signal transition onto a control pad of a semiconductor chip wit... | 08/16/2005 |
| 6927595 | Dynamically switched voltage screen This invention teaches an apparatus and method for determining a more efficient quality assurance or reliability test screen without falsely rejecting, i.e., over stressing, short channel length devices during voltage stress test screening. Short channel lengths dev... | 08/09/2005 |
| 6922076 | Scalable termination In a first aspect, a first method is provided for providing multiple termination values using a plurality of binary termination signals. The first method includes the steps of (1) determining a characteristic impedance of a first port by generating a plurality of bi... | 07/26/2005 |
| 6921288 | Semiconductor test and burn-in apparatus provided with a high current power connector for combining power planes A semi-conductor module burn-in test apparatus having a plurality burn-in boards each of which is provided a plurality of module test sockets thereon and each test socket is coupled to an adjacent test socket by with a high current, open/short split power connector ... | 07/26/2005 |
| 6920525 | Method and apparatus of local word-line redundancy in CAM A local word-line redundancy architecture and method that implements both word-line and match-line steering for semiconductor memories and more particularly for content-addressable memories (CAM) are introduced. According to the present invention, the method of perf... | 07/19/2005 |
| 6912665 | Automatic timing analyzer A test methodology is used to conduct an automatic chip timing analysis in coarse and fine resolution steps. Timing adjustment circuits implement coarse timing adjustment and fine timing adjustment for chip timing analysis. Timings such as clock, address and control... | 06/28/2005 |
| 6909274 | Signal pin tester for AC defects in integrated circuits A test apparatus and a method for testing an integrated circuit's data storage device's input/output signal pins for alternating current (AC) defects, by providing an interface that will couple each respective individual test contact, in a subset of said contacts, t... | 06/21/2005 |
| 6909296 | Wafer level system for producing burn-in/screen, and reliability evaluations to be performed on all chips simultaneously without any wafer contacting A wafer level system for producing burn-in, voltages screen, and reliability evaluations which are to be performed on all wafers simultaneously without necessitating the probe contacting of any wafer during burn-in/stress. Also provided is a method for implementing ... | 06/21/2005 |
| 6901542 | Internal cache for on chip test data storage A method of testing a semiconductor device having a memory is disclosed. The method includes selecting a portion of the memory; testing the selected portion of the memory; designating the selected portion of the memory as a designated memory in response to an accept... | 05/31/2005 |
| 6897674 | Adaptive integrated circuit based on transistor current measurements A method of tuning an integrated circuit on an integrated circuit chip including: performing a drain current at saturation measurement of one or more test field effect transistors on the integrated circuit chip; selectively programming fuses of a bank of fuses on th... | 05/24/2005 |
| 6888714 | Tuneable ferroelectric decoupling capacitor A voltage supply bypass capacitor for use with a semiconductor integrated circuit chip or module comprising a ferroelectric dielectric having electromechanical properties designed to provide maximum losses at selected frequencies. ... | 05/03/2005 |
| 6888187 | DRAM cell with enhanced SER immunity A memory cell that has first and second fully depleted transfer devices each having a body region and first and second diffused electrodes. The cell has a differential storage capacitor having at least one node abutting and in electrical contact with one of the firs... | 05/03/2005 |
| 6882159 | Associated grouping of embedded cores for manufacturing test A structure and associated method for associated grouping of an alpha device with a plurality of dependent devices for a manufacturing test. The alpha device comprises at least one electrical characteristic. The plurality of dependent devices each comprise the at le... | 04/19/2005 |
| 6880136 | Method to detect systematic defects in VLSI manufacturing Defects in manufacturing of IC devices are analyzed by testing the devices for defects using results of LSSD technology to find at least one failing pattern that contains incorrect values. The failing latches are used as a starting point to trace back through combin... | 04/12/2005 |
| 6865501 | Using clock gating or signal gating to partition a device for fault isolation and diagnostic data collection In one aspect, an electronic device that has been partitioned into segments by using clock gating or signal gating is tested. One of the segments that is a source of a failure is identified. Diagnostic procedures are applied to the identified segment to determine a ... | 03/08/2005 |
