Did You Know...
...that Charles Goodyear performed some of his experiments on rubber while in debtor's prison? He was there so often he referred to it as his "hotel". Chronically in debt because of poor business sense and ill health, Goodyear depended on the generosity of friends and family. Even after he unlocked the secret to vulcanizing rubber, he was unable to improve his financial situation. When he died, his estate was $200,000 in debt.
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| Number | Title | Issue Date |
| 8184696 | Method and apparatus for an adaptive systolic array structure A method and apparatus for an adaptive systolic array structure is initially configured for motion estimation calculations and optionally reconfigured as the motion estimation algorithm progresses. A scheduling map of the processing element (PE) calculations for a g... | 05/22/2012 |
| 8165845 | Method and apparatus for statistical identification of devices based on parametric data A method and apparatus is provided for the calculation of maverick control limits. The maverick control limit method selects the correct parameter(s) as critical parameters to be utilized by the maverick control limit method. Next, the maverick control limit method ... | 04/24/2012 |
| 8130027 | Apparatus and method for the detection and compensation of integrated circuit performance variation An apparatus and method for the dynamic detection and compensation of performance variations within an integrated circuit (IC) is provided to detect performance variations within the IC at any stage of test or operation. An arbitrary reference signal is utilized in ... | 03/06/2012 |
| 8120075 | Semiconductor device with improved trenches A semiconductor device exhibiting enhanced carrier mobility within a channel region of the semiconductor device is disclosed. The semiconductor device includes a gate stack having first and second sidewall spacers, where the gate stack is implemented above the chann... | 02/21/2012 |
| 8117497 | Method and apparatus for error upset detection and correction A method and apparatus for the detection and correction of soft errors existing within an integrated circuit (IC). Run-time check stops are utilized in conjunction with processor-based, hardware mechanisms to detect and correct soft errors. At run-time, each check s... | 02/14/2012 |
| 8091056 | Apparatus and method for automated determination of timing constraints A method and apparatus is provided for the automatic creation of timing constraints that are based upon input interface timing parameters entered through a graphical user interface that is associated with the one or more input interfaces. Ideal timing constraints ar... | 01/03/2012 |
| 8090335 | Method and apparatus for an adaptive step frequency calibration An open loop frequency calibration algorithm is employed whereby frequency counters are utilized to provide frequency information concerning the difference in frequency between a local oscillator and a reference signal prior to obtaining phase locked operation of a ... | 01/03/2012 |
| 8058924 | Method and apparatus for a process, voltage, and temperature variation tolerant semiconductor device A method and apparatus to reduce the degradation in performance of semiconductor-based devices due to process, voltage, and temperature (PVT) and/or other causes of variation. Adaptive feedback mechanisms are employed to sense and correct performance degradation, wh... | 11/15/2011 |
| 8032852 | Method of automating clock signal provisioning within an integrated circuit A method is provided to incorporate information currently known about an integrated circuit's design, including peripheral components that share the same printed circuit board (PCB) with the integrated circuit, to automate a clock signal instantiation and routing so... | 10/04/2011 |
| 7978802 | Method and apparatus for a mesochronous transmission system A method and apparatus for a multiple lane transmission system that provides both a low latency mode of operation, while at the same time, provides reduced lane-lane skew. The overall transmission system operates as a mesochronous system, whereby each clock domain o... | 07/12/2011 |
| 7970090 | Method and apparatus for a self-synchronizing system A self-synchronizing system that provides a master system component and a master clock source to provide a stable timing reference to the master system component. Timing information is then propagated throughout the system via encoded transmissions containing the ti... | 06/28/2011 |
| 7951722 | Double exposure semiconductor process for improved process margin A double exposure semiconductor process is provided for improved process margin at reduced feature sizes. During a first processing sequence, features defining non-critical dimensions of a polysilicon interconnect structure are formed, while other portions of the po... | 05/31/2011 |
| 7924912 | Method and apparatus for a unified signaling decision feedback equalizer A method and apparatus for advantageously utilizing the reset state of an RTZ shift register to guarantee proper data alignment at the feedback taps to facilitate decision feedback equalization (DFE) in a unified signaling system. An input data stream is sliced into... | 04/12/2011 |
| 7913104 | Method and apparatus for receive channel data alignment with minimized latency variation Data and clock synchronization within a gigabit receiver is maintained throughout the data byte processing logic of the receiver by utilizing the same byte clock signal. The deserialization clock signal that is used to deserialize the received serial data stream is ... | 03/22/2011 |
| 7904761 | Method and apparatus for a discrete power series generator A method and apparatus for the generation of discrete power series values (PSVs) and associated PSV addresses. Repeated evaluations of a discrete power series are performed by a reduced complexity PSV generator, such that the need for multiplication operations is ob... | 03/08/2011 |
| 7888954 | Method of utilizing an interposer in an automated test system and an automated test system having an interposer A method and apparatus is provided to facilitate testing of integrated circuits using an interposer to be utilized in conjunction with an automated test equipment (ATE) system that includes a device handler and a device tester. The interposer may be utilized to conv... | 02/15/2011 |
| 7888143 | Apparatus and method for characterizing structures within an integrated circuit An apparatus and method of utilizing an electron beam and ion beam microscope in combination with nanomanipulators to improve the accuracy of the characterization of structures within an integrated circuit. Probes attached to the nanomanipulators, i.e., nano-probes,... | 02/15/2011 |
| 7859918 | Method and apparatus for trimming die-to-die variation of an on-chip generated voltage reference A method and apparatus is provided for the implementation of a measurement and adjustment mechanism within a semiconductor die that facilitates adjustment of the magnitude of voltage generated by one or more voltage reference generation circuits on the die. In a fir... | 12/28/2010 |
| 7851313 | Semiconductor device and process for improved etch control of strained silicon alloy trenches A semiconductor process for improved etch control in which an anisotropic selective etch is used to better control the shape and depth of trenches formed within a semiconductor material. The etchants exhibit preferential etching along at least one of the crystallogr... | 12/14/2010 |
| 7830986 | Method and apparatus for a phase/frequency locked loop A phase/frequency detector module allows operation as either a phase locked loop or a frequency locked loop. As a phased locked loop (PLL), the phase detector module is configured to decode phase differences between a reference signal and a voltage controlled oscill... | 11/09/2010 |
| 7809864 | Method and apparatus for a hot-swappable input/output device with programmable over-voltage clamp protection A method and apparatus is provided for a configurable input/output (I/O) interface within an integrated circuit to support a plurality of I/O standards. The configurable I/O interface exhibits a default operation that facilitates hot-swappability, which eliminates c... | 10/05/2010 |
| 7786782 | Method and apparatus for counter-based clock signal adaptation A method and apparatus to implement clock signal adaptation is provided to characterize an input clock signal that is to be adapted and in response, generate adaptation updates at each subsequent clock cycle of the input clock signal. In a first embodiment, clock si... | 08/31/2010 |
| 7782702 | Apparatus and method for memory cell power-up sequence A method and apparatus is provided to enhance the power-up sequence for integrated circuits (ICs) that contain memory cells having single-ended data inputs with no local reset function. During a power-up sequence, the logic levels that are applied to the data, addre... | 08/24/2010 |
| 7761776 | Method and apparatus for a modular, programmable cyclic redundancy check design A linear feedback shift register (LFSR) based design is applied to cyclic redundancy check (CRC) modules, in which a CRC building block having a minimum width is implemented. The CRC building block accepts a generator polynomial as an input design parameter to build... | 07/20/2010 |
| 7761276 | Apparatus and method for port reduction in simulation files Various port reduction methods are employed to reduce the number of port definitions in a simulation file. A ground port reduction method is first employed to reduce certain power supply reference connections to an absolute ground reference for the circuit model. Ne... | 07/20/2010 |
| 7742553 | VCO initial frequency calibration circuit and method therefore A device and a method for processing high data rate serial data includes a VCO initial frequency calibration circuit. The circuit includes a frequency detection block for indicating a difference between a reference clock and a divided VCO clock, a frequency calibrat... | 06/22/2010 |
| 7728630 | Method and apparatus for a process, voltage, and temperature variation tolerant semiconductor device A method and apparatus to reduce the degradation in performance of semiconductor-based devices due to process, voltage, and temperature (PVT) and/or other causes of variation. Adaptive feedback mechanisms are employed to sense and correct performance degradation, wh... | 06/01/2010 |
| 7724815 | Method and apparatus for a programmably terminated receiver A method and apparatus for a receive equalizer of a gigabit transceiver that is reconfigurable to support multiple communication standards. Communication standards having variable common mode and coupling requirements are accommodated through the use of reconfigurab... | 05/25/2010 |
| 7701245 | Enhanced voltage regulation with power supply disable capability for low-power operation A method and apparatus is provided that facilitates low-power consumption during a suspend mode of operation of an integrated circuit (IC), while substantially eliminating current paths within the IC that may be created should any of the power supplies be deactivate... | 04/20/2010 |
| 7671624 | Method to reduce configuration solution using masked-ROM A packaged PLD solution includes a first die having a masked-Read Only Memory (ROM) that is programmed during its fabrication to store configuration data, and includes a second die having a PLD including a number of configurable resources collectively configured to ... | 03/02/2010 |
| 7668238 | Method and apparatus for a high speed decision feedback equalizer A method and apparatus for advantageously utilizing the reset state of an RTZ shift register to guarantee proper data alignment at the feedback taps to facilitate decision feedback equalization (DFE). An input data stream (DATA) is sliced into an even data stream an... | 02/23/2010 |
| 7653505 | Method and apparatus for testing a controlled impedance buffer A method and apparatus is provided to utilize the configurability of a programmable logic device (PLD), so as to reduce the complexity of special test equipment (STE) fixtures that are required to test the PLD. The output drivers of certain I/O buffers of the PLD th... | 01/26/2010 |
| 7653127 | Bit-edge zero forcing equalizer Bit-Edge Zero Forcing Equalizer. A novel solution is presented by which a BE-ZFE (Bit-Edge Zero Forcing Equalizer) is employed to drive an error term within a data signal to an essentially zero value. This new BE-ZFE looks at values of data that occur at the bit edg... | 01/26/2010 |
| 7639735 | Method and apparatus for signal to noise ratio estimation A method and apparatus for generating a signal to noise ratio (SNR) estimate. A conditional probability distribution function (CPDF) is rectified to suppress the condition, thereby creating a biased CPDF. Conditional offset moments are computed through an analysis o... | 12/29/2009 |
| 7628409 | Method and apparatus for an electronic equipment rack A method and apparatus for an electronic equipment rack that provides mobility through directional self-propulsion and multi-axis suspension. The electronic equipment rack further provides self-powered operation and environmental control with wireless access, while ... | 12/08/2009 |
| 7614022 | Testing for bridge faults in the interconnect of programmable integrated circuits Apparatus and methods of testing for bridge faults in nets of the interconnect of a programmable integrated circuit. Each net is sourced by a function generator (e.g., a look up table) configured as a clocked shift register. For each net group, shift registers conne... | 11/03/2009 |
| 7613990 | Method and system for a multi-channel add-compare-select unit A circuit for a multi-channel add-compare-select unit is disclosed. The circuit includes a compare unit and a datapath. The datapath is coupled to the compare unit, and includes a number of adder units, a selection unit (which is coupled to the adder units), and a n... | 11/03/2009 |
| 7611157 | Method and apparatus for an electronic equipment rack A method and apparatus for an electronic equipment rack that provides mobility through directional self-propulsion and multi-axis suspension. The electronic equipment rack further provides self-powered operation and environmental control with wireless access, while ... | 11/03/2009 |
| 7605460 | Method and apparatus for a power distribution system A method and apparatus is provided to reduce the spreading inductance and increase the distributed capacitance of power planes within the power distribution system of a semiconductor package substrate. In one embodiment, pre-fabricated copper-clad laminate (CCL) str... | 10/20/2009 |
| 7600204 | Method for simulation of negative bias and temperature instability An apparatus and method to accurately simulate negative bias and temperature instability (NBTI) and its effect. According to a first simulation method, a simulation netlist is automatically scanned for any P-type devices that are in a conductive state after applicat... | 10/06/2009 |
