WILLIAMS, MORGAN & AMERSON - US Patent Attorneys and Agents

Attorney: WILLIAMS, MORGAN & AMERSON

Number of patents: 49
Last date: May 22, 2012

Number	Title	Issue Date
8185230	Method and apparatus for predicting device electrical parameters during fabrication A method includes providing a set of initial characteristic values associated with the semiconductor device. A first fabrication process is performed on the semiconductor device. Fabrication data associated with the first fabrication process is collected. At least o...	05/22/2012
8185226	Method and system for scheduling a stream of products in a manufacturing environment by using process-specific WIP limits By defining a section-related WIP limit or a throughput-related WIP limit, an efficient “look ahead” characteristic may be established to efficiently control the WIP in a complex manufacturing environment, such as a semiconductor facility. The respective critica...	05/22/2012
8183605	Reducing transistor junction capacitance by recessing drain and source regions By recessing portions of the drain and source areas on the basis of a spacer structure, the subsequent implantation process for forming the deep drain and source regions may result in a moderately high dopant concentration extending down to the buried insulating lay...	05/22/2012
8183139	Reduced defectivity in contacts of a semiconductor device comprising replacement gate electrode structures by using an intermediate cap layer Superior contact elements may be formed in semiconductor devices in which sophisticated replacement gate approaches may be applied. To this end, a dielectric cap layer is provided prior to patterning the interlayer dielectric material so that any previously created ...	05/22/2012
8183101	Multiple gate transistor having fins with a length defined by the gate electrode The drain and source regions of a multiple gate transistor may be formed without an epitaxial growth process by using a placeholder structure for forming the drain and source dopant profiles and subsequently masking the drain and source areas and removing the placeh...	05/22/2012
8183100	Transistor with embedded SI/GE material having enhanced across-substrate uniformity In sophisticated semiconductor devices, a strain-inducing semiconductor alloy may be positioned close to the channel region by forming cavities on the basis of a wet chemical etch process, which may have an anisotropic etch behavior with respect to different crystal...	05/22/2012
8183096	Static RAM cell design and multi-contact regime for connecting double channel transistors A static RAM cell may be formed on the basis of two double channel transistors and a select transistor, wherein a body contact may be positioned laterally between the two double channel transistors in the form of a dummy gate electrode structure, while a further rec...	05/22/2012
8170704	Method and system for automatic generation of throughput models for semiconductor tools The throughput of complex cluster tools of a semiconductor manufacturing environment may be determined for a desired manufacturing scenario on the basis of automatically generated throughput models. The throughput models may be established on the basis of rule messa...	05/01/2012
8163594	Semiconductor device comprising a carbon-based material for through hole vias In a semiconductor device, a through hole via extending through the substrate of the device may be formed on the basis of a carbon-containing material, thereby providing excellent compatibility with high temperature processes, while also providing superior electrica...	04/24/2012
8163571	Multi-step deposition control For providing control of two-step or a multi-step deposition process, a method and a corresponding deposition system is provided comprising providing a deposition process having at least two sub-processes employing different sets of process parameters, wherein each ...	04/24/2012
8158065	In situ monitoring of metal contamination during microstructure processing By providing a tool internal sensor device in a process tool in a semiconductor facility, metal contamination may be monitored in situ, thereby avoiding or at least significantly reducing the requirement for sophisticated sample preparation techniques, such as vapor...	04/17/2012
8153524	Providing superior electromigration performance and reducing deterioration of sensitive low-k dielectrics in metallization systems of semiconductor devices During the formation of complex metallization systems, a conductive cap layer may be formed on a copper-containing metal region in order to enhance the electromigration behavior without negatively affecting the overall conductivity. At the same time, a thermo chemic...	04/10/2012
8152595	System and method for optical endpoint detection during CMP by using an across-substrate signal In a polishing process, the characteristics of the removal process may be monitored at different lateral positions to identify the clearance of the various device regions with a high degree of reliability. Consequently, upon forming sophisticated metallization struc...	04/10/2012
8143133	Technique for enhancing dopant profile and channel conductivity by millisecond anneal processes During the fabrication of advanced transistors, significant dopant diffusion may be suppressed by performing a millisecond anneal process after completing the basic transistor configuration, wherein a stress memorization technique may also be obtained by forming a s...	03/27/2012
8126588	Method and system for controlling transport sequencing in a process tool by a look-ahead mode By providing a look-ahead functionality for a tool internal substrate handling system of process tools on the basis of a process history, the tool internal substrate sequencing may be significantly enhanced. The look-ahead functionality enables a prediction of proce...	02/28/2012
8114688	Method and semiconductor structure for monitoring etch characteristics during fabrication of vias of interconnect structures By forming a trench-like test opening above a respective test metal region during the etch process for forming via openings in a dielectric layer stack of sophisticated metallization structures of semiconductor devices, the difference in etch rate in the respective ...	02/14/2012
8086216	Mobility aware policy and charging control in a wireless communication network One embodiment of the present invention provides a method for implementation in a policy control and charging rules functional entity in a wireless communication system. The method includes receiving, from at least one of a source policy and charging enforcement fun...	12/27/2011
8084354	Method of fabricating a metal cap layer with enhanced etch resistivity for copper-based metal regions in semiconductor devices During the fabrication of sophisticated metallization systems of semiconductor devices, material deterioration of conductive cap layers may be significantly reduced by providing a noble metal on exposed surface areas after the patterning of the corresponding via ope...	12/27/2011
8084088	Method of improving the wafer-to-wafer thickness uniformity of silicon nitride layers Wafer-to-wafer thickness uniformity may be improved significantly in a process for depositing a silicon nitride layer in that the flow rate of the reactant and the chamber pressure are varied during a deposition cycle. By correspondingly adapting the flow rate and/o...	12/27/2011
8068846	Method of assigning a mobile unit to a tracking area based on a location update frequency The present invention provides a method for assigning a mobile unit to a tracking area based upon a location update frequency. The method includes selecting one of a technology-specific tracking area and a shared tracking area based on a location update frequency as...	11/29/2011
8062982	High yield plasma etch process for interlayer dielectrics A high yield plasma etch process for an interlayer dielectric layer of a semiconductor device is provided, according to an embodiment of which a dielectric layer is etched with a nitrogen-containing plasma. In this way, the formation of polymers on a backside bevel ...	11/22/2011
8062952	Strain transformation in biaxially strained SOI substrates for performance enhancement of P-channel and N-channel transistors In advanced SOI devices, a high tensile strain component may be achieved on the basis of a globally strained semiconductor layer, while at the same time a certain compressive strain may be induced in P-channel transistors by appropriately selecting a height-to-lengt...	11/22/2011
8060882	Processing tasks with failure recovery A method and apparatus is provided for processing tasks with failure recovery. The method includes storing one or more tasks in a queue, wherein each task has an associated exit routine, and determining at least one task to process based on a priority scheme. The me...	11/15/2011
8058731	Technique for forming metal lines in a semiconductor by adapting the temperature dependence of the line resistance By moderately introducing defects into a highly conductive material, such as copper, the resistance versus temperature behavior may be significantly modified so that enhanced electromigration behavior and/or electrical performance may be obtained in metallization st...	11/15/2011
8054826	Controlling service quality of voice over Internet Protocol on a downlink channel in high-speed wireless data networks The present invention provides a method and an apparatus for controlling service quality of data communications in a wireless network in which quality of service control for voice over internet protocol packets is provided on a downlink shared channel. A method is p...	11/08/2011
8053273	Shallow PN junction formed by in situ doping during selective growth of an embedded semiconductor alloy by a cyclic growth/etch deposition process A silicon/carbon alloy may be formed in drain and source regions, wherein another portion may be provided as an in situ doped material with a reduced offset with respect to the gate electrode material. For this purpose, in one illustrative embodiment, a cyclic epita...	11/08/2011
8051301	Memory management system and method providing linear address based memory access security A memory management unit (MMU) is disclosed for managing a memory storing data arranged within a plurality of memory pages. The MMU includes a security check unit (SCU) receiving a linear address generated during execution of a current instruction. The linear addres...	11/01/2011
8048748	Reducing contamination in a process flow of forming a channel semiconductor alloy in a semiconductor device In sophisticated approaches for forming high-k metal gate electrode structures in an early manufacturing stage, a threshold adjusting semiconductor alloy may be deposited on the basis of a selective epitaxial growth process without affecting the back side of the sub...	11/01/2011
8047762	Method and system for locally buffering substrate carriers in an overhead transport system for enhancing input/output capabilities of process tools By providing an overhead buffer system between an automatic transport system and a load port assembly of a process tool, the efficiency of the respective load ports may be significantly enhanced, for instance, by reducing the idle time of empty carriers, thereby pro...	11/01/2011
8039958	Semiconductor device including a reduced stress configuration for metal pillars In a metallization system of a sophisticated semiconductor device, metal pillars may be provided so as to exhibit an increased efficiency in distributing any mechanical stress exerted thereon. This may be accomplished by significantly increasing the surface area of ...	10/18/2011
8039335	Semiconductor device comprising NMOS and PMOS transistors with embedded Si/Ge material for creating tensile and compressive strain By forming a substantially continuous and uniform semiconductor alloy in one active region while patterning the semiconductor alloy in a second active region so as to provide a base semiconductor material in a central portion thereof, different types of strain may b...	10/18/2011
8039181	Method and system for reducing overlay errors in semiconductor volume production using a mixed tool scenario By taking into consideration the combination of the substrate holders in various lithography tools used during the imaging to two subsequent device layers, enhanced alignment accuracy may be accomplished. Furthermore, restrictive tool dedications for critical lithog...	10/18/2011
8035196	Methods of counter-doping collector regions in bipolar transistors The present invention provides a method of forming a bipolar transistor. The method includes doping a silicon layer with a first type of dopant and performing a first implant process to implant dopant of a second type opposite the first type in the silicon layer. Th...	10/11/2011
8018260	Compensation of degradation of performance of semiconductor devices by clock duty cycle adaptation The device degradation of integrated circuits may be compensated for by appropriately adapting the duty cycle of the clock signal. For this purpose, a correlation between the duty cycle and the overall performance characteristics of the integrated circuit may be est...	09/13/2011
8012775	Method of forming a light activated silicon controlled switch The present invention provides a method of forming an optically triggered switch. Embodiments of the method include forming a silicon layer, forming one or more trenches in the silicon layer, and forming one or more silicon diodes in the silicon layer. Embodiments o...	09/06/2011
7986040	Method of reducing erosion of a metal cap layer during via patterning in semiconductor devices During the patterning of via openings in sophisticated metallization systems of semi-conductor devices, the opening may extend through a conductive cap layer and an appropriate ion bombardment may be established to redistribute material of the underlying metal regio...	07/26/2011
7977179	Dopant profile tuning for MOS devices by adapting a spacer width prior to implantation By selectively modifying the spacer width, for instance, by reducing the spacer width on the basis of implantation masks, an individual adaptation of dopant profiles may be achieved without unduly contributing to the overall process complexity. For example, in sophi...	07/12/2011
7974801	Method and system for a two-step prediction of a quality distribution of semiconductor devices By performing a two-step approach for predicting a quality distribution during the fabrication of semiconductor devices, enhanced flexibility and efficiency may be accomplished. The two-step approach first models electrical characteristics on the basis of measuremen...	07/05/2011
7974726	Method and system for removing empty carriers from process tools by controlling an association between control jobs and carrier By providing an under-specified specification for designating a destination carrier in a respective control job or control message, a high degree of flexibility in determining the destination of processed substrates may be obtained, thereby also allowing the removal...	07/05/2011
7536233	Method and apparatus for adjusting processing speeds based on work-in-process levels The present invention provides a method and apparatus for adjusting tool processing speeds based on work-in-process levels. The method includes determining at least one work-in-process level associated with a first processing tool and modifying a processing speed as...	05/19/2009

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