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| Number | Title | Issue Date |
| 8044484 | Ultraviolet detecting device and manufacturing method thereof, and ultraviolet quantity measuring apparatus The present invention provides an ultraviolet detecting device which comprises a silicon semiconductor layer having a thickness ranging from greater than or equal to 3 nm to less than or equal to 36 nm, which is formed over an insulating layer, lateral PN-junction t... | 10/25/2011 |
| 7985638 | Method of manufacturing semiconductor device A semiconductor device manufacturing method which sequentially forms a gate oxide film and gate electrode material over a semiconductor layer of an SOI substrate and patterns the material into gate electrodes. The method further comprises the steps of forming sidewa... | 07/26/2011 |
| 7957950 | Hard/soft cooperative verifying simulator A hard/soft cooperative verifying simulator is based on a SystemC simulator, and provides the capability of reducing overhead of context switching control thereby to shorten processing time. Time keepers for controlling simulation times of a plurality of threads are... | 06/07/2011 |
| 7956784 | DA converter including conversion amplifier having output voltage with improved linearity A DA converter includes an IV conversion amplifier with output voltage having good linearity, to thus improve total harmonic distortion (THD) characteristics. In the DA converter, a first current path in which current flows due to differential switches being in the ... | 06/07/2011 |
| 7956430 | Semiconductor device including groove width variation portion for inspection An accelerator sensor includes a semiconductor substrate having a main front surface and a main rear surface, a first groove portion being formed along a front surface pattern, in the main front surface, a second groove portion being formed along a rear surface patt... | 06/07/2011 |
| 7955933 | Method of manufacturing nonvolatile semiconductor memory device A method of manufacturing a nonvolatile semiconductor memory device includes the steps of preparing a wafer having multiple memory cells, each memory cell having a gate electrode formed on a semiconductor substrate, charge storage units formed on both sides of the g... | 06/07/2011 |
| 7952118 | Semiconductor device having different metal gate structures A semiconductor includes a channel region in a semiconductor substrate, a gate dielectric film on the channel region, and a gate on the gate dielectric film. The gate includes a doped metal nitride film, formed from a nitride of a first metal and doped with a second... | 05/31/2011 |
| 7948794 | Nonvolatile memory device using variable resistive element A nonvolatile memory device includes multiple memory blocks divided into multiple memory block groups. Each memory block group includes at least two memory blocks of the multiple memory blocks. The nonvolatile memory device also includes a main word line common to t... | 05/24/2011 |
| 7948300 | Negative supply voltage generating circuit and semiconductor integrated circuit having the same A negative supply voltage generating circuit includes a pulse generating circuit and a charge pump. The pulse generating circuit generates a first pulse signal and a second pulse signal in response to a clock signal. The first and second pulse signals have pulse wid... | 05/24/2011 |
| 7948278 | Load capacity driving circuit The present invention provides a load capacity driving circuit that is inexpensive and has a high driving capability. When an input signal changes to low potential, gate voltage of an output stage of an amplifying circuit increases, an NMOS transistor MNO turns on, ... | 05/24/2011 |
| 7947563 | Chip ID applying method suitable for use in semiconductor integrated circuit A chip forming position specifying method for applying chip IDs indicative of positions on a wafer where semiconductor chips are formed, and thereby specifying their positions. In the chip forming position specifying method, different marks are formed for every chip... | 05/24/2011 |
| 7945062 | Microelectromechanical microphone packaging system The invention relates to a microelectromechanical microphone packaging system. The microelectromechanical microphone packaging system comprises a substrate, a chip, a microelectromechanical microphone, a conductive glue, a non-conductive glue and a cover. The substr... | 05/17/2011 |
| 7944747 | Flash memory device and method for programming flash memory device having leakage bit lines Provided is a method for programming a flash memory device. The method includes receiving writing data, detecting leakage bit lines of the flash memory device, and updating the received writing data in order for data corresponding to the leakage bit lines to be modi... | 05/17/2011 |
| 7944058 | Semiconductor device and process for fabricating the same A thin stacked semiconductor device has a plurality of circuits that are laminated and formed sequentially in a specified pattern to form a multilayer wiring part. At the stage for forming the multilayer wiring part, a filling electrode is formed on the semiconducto... | 05/17/2011 |
| 7939379 | Hybrid carrier and a method for making the same A hybrid carrier and a method for making the same, wherein the hybrid carrier has a plurality of interconnection leads, so that a wire bondable semiconductor device or a flip chip die apparatus can be placed on the hybrid carrier, and is electrically connected to di... | 05/10/2011 |
| 7936232 | Substrate for semiconductor package A substrate for a semiconductor package includes a dielectric substrate, a circuit pattern formed on a first surface of the dielectric substrate, and an electromagnetic band gap (EGB) pattern. The EGB pattern includes multiple unit structures formed on a second surf... | 05/03/2011 |
| 7932597 | Semiconductor device and manufacturing method thereof A BGA substrate which has a back surface to which a heat radiating plate is attached and an opening for accommodating a relay wiring substrate therein, which is provided in the center of its surface, is used. The relay wiring substrate to which an ASIC chip and a me... | 04/26/2011 |
| 7927951 | Non-volatile memory device and method of operating the same A non-volatile memory device includes a semiconductor substrate, first and second control gates, and first and second charge storage patterns. The semiconductor substrate includes a protruding active pin having a source region, a drain region and a channel region lo... | 04/19/2011 |
| 7927499 | Substrate having blind hole and method for forming blind hole A substrate having a blind hole and a method for forming the blind hole. The method includes: (a) providing a substrate having a lower dielectric layer, a copper layer, and an upper dielectric layer; and (b) forming an upper dielectric layer through hole and a coppe... | 04/19/2011 |
| 7924644 | Semiconductor memory device including floating body transistor memory cell array and method of operating the same A semiconductor memory device includes a memory cell array including a plurality of memory cells, where each memory cell includes a transistor with a floating body region in which majority carriers are accumulated in a steady state. In write and read operations, a f... | 04/12/2011 |
| 7923997 | Magneto-sensitive integrated circuit A magneto-sensitive integrated circuit which amplifies a magneto-sensitive output voltage of a Hall element by an amplifier to generate an amplified voltage, converts an output voltage of the amplifier into a digital signal by an A/D converter; and generates a refer... | 04/12/2011 |
| 7917733 | Instruction code compression using instruction codes with reuse flags An instruction code compression method and an instruction fetch circuit which are capable of reducing both the number of fetches and program codes. A reuse flag is provided in an upper bit group including operational codes, and a lower bit group including operands a... | 03/29/2011 |
| 7916542 | Nonvolatile memory device with multiple page regions, and methods of reading and precharging the same A nonvolatile memory device includes a memory cell array having multiple memory cells arranged at intersections of word lines and bit lines, a first page region configured with at least two adjacent memory cells coupled to a word line, and a second page region confi... | 03/29/2011 |
| 7915746 | Semiconductor wafer, and semiconductor device formed therefrom A semiconductor wafer has a substrate, and a plurality of active areas formed on the substrate. Integrated circuits are formed in the active areas. The semiconductor wafer also has dicing areas formed between the adjacent active areas. A seal ring is formed along th... | 03/29/2011 |
| 7915119 | Semiconductor memory device and manufacturing method thereof An active region is provided which includes a plurality of active region columns extending in a first direction and a plurality of active region rows extending in a second direction substantially orthogonal to the first direction and having concave portions. Floatin... | 03/29/2011 |
| 7911056 | Substrate structure having N-SMD ball pads A substrate structure having non-solder mask design (N-SMD) ball pads. The substrate structure includes a substrate and a solder mask. The substrate has a first surface, a trace layer and at least one ball pad. The ball pad and the trace layer are disposed on the fi... | 03/22/2011 |
| 7910862 | Apparatus and method for manufacturing a semiconductor device with a sapphire substrate A supporting base, including a supporting plate and holders, holds a sapphire substrate so that one substrate surface faces a hot plate and the other substrate surface faces a radiant heat absorbing plate mounted on the supporting plate. Radiant heat from the hot pl... | 03/22/2011 |
| 7907454 | Method of verifying programming operation of flash memory device A method is provided for verifying a programming operation of a flash memory device. The flash memory device includes at least one memory string in which a string selection transistor, multiple memory cells and a ground selection transistor are connected in series, ... | 03/15/2011 |
| 7907441 | Data management method and mapping table update method in non-volatile memory device A data management method of a non-volatile memory device includes writing data and representing a state of the data. The state includes one of multiple possible states. A state of the multiple possible states corresponding to a final operation is determined as a val... | 03/15/2011 |
| 7904866 | Computer readable recording medium with a wiring design program stored thereon and wiring design device An apex is extracted from a designed wiring layout. In start/end portion circular arc processing a circular arc is added to the apex-containing portion, and the layout data file is rewritten so that a portion, representing a region surrounded by circular arc and two... | 03/08/2011 |
| 7902645 | Semiconductor device, semiconductor element, and substrate A semiconductor device, a semiconductor element, and a substrate are provided, which allow the semiconductor element to be provided with a reduced size when combined. The semiconductor device has a rectangular semiconductor element mounted on a substrate formed with... | 03/08/2011 |
| 7893877 | Antenna for WWAN and integrated antenna for WWAN, GPS and WLAN An integrated antenna for WWAN, GPS, and WLAN includes a ground metal plane, a WWAN antenna, and a WLAN antenna. The WWAN antenna is connected to the ground metal plane and includes first and second radiating metal strips which induce a first resonance mode and a se... | 02/22/2011 |
| 7893530 | Circuit substrate and the semiconductor package having the same The present invention relates to a circuit substrate comprising an upper surface, a first layout area, a second layout area, and a third layout area. The first layout area is on the upper surface, and has a plurality of first electrical contacts. The second layout a... | 02/22/2011 |
| 7892918 | Method of fabricating a semiconductor device including formation of contact holes A wiring structure in a semiconductor device includes a first insulation layer formed on a substrate having first and second contact regions, and first and second pads extending through the first insulation layer and contacting the first and the second contact regio... | 02/22/2011 |
| 7885136 | Semiconductor memory device having high stability and quality of readout operation A semiconductor memory cell device includes a first multiplexer selecting a sub-block including a memory cell storing data to be read out in a row, a drain selector selecting a first column line connected to one terminal of the memory cell to be read, a precharge se... | 02/08/2011 |
| 7885118 | Flash memory device and voltage generating circuit for the same Disclosed is a flash memory device which includes a memory core, a high voltage generating circuit and a reference voltage generating circuit. The high voltage generating circuit is configured to generate a high voltage to be supplied to the memory core. The referen... | 02/08/2011 |
| 7885111 | Flash memory device and method for providing initialization data A flash memory device includes a cell array and a decision unit. The cell array includes multiple regions corresponding to multiple input/output lines. Initialization data are repeatedly stored in each of the regions. The decision unit determines whether the stored ... | 02/08/2011 |
| 7884400 | Image device and method of fabricating the same An image device and a method of fabricating the image device include a substrate pattern formed to define an opening and to include a portion of a photodiode for receiving light. Stacked metal interconnection patterns and an interlayer dielectric layer are formed be... | 02/08/2011 |
| 7884008 | Semiconductor device fabrication method A method of forming a semiconductor device including a semiconductor substrate with circuit elements and electrode pads formed on one surface. This surface is covered by a dielectric layer with openings above the electrode pads. A metal layer is deposited on the die... | 02/08/2011 |
| 7879657 | Semiconductor device and manufacturing method thereof An insulating film layer is formed between a channel region of an MOS element formed in a monocrystal silicon layer of an SOS substrate in which the monocrystal silicon layer is laminated on a sapphire substrate, and the sapphire substrate, thereby to bring a stress... | 02/01/2011 |
