Celebrity Inventors
Glam girl Heddy Lamar may have used her good looks to good effect on the silver screen, but she put her smarts to better use as an inventor. During World War II, she co-patented a frequency-switching system for torpedo guidance that was considered years ahead of its time.
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| Number | Title | Issue Date |
| 7535766 | Systems for partitioned soft programming in non-volatile memory Soft programming is performed to narrow the threshold voltage distribution of a set of erased memory cells. Soft programming can shift the threshold voltage of memory cells closer to a verify level for the erased state. A set of memory cells can be soft programmed b... | 05/19/2009 |
| 7535764 | Adjusting resistance of non-volatile memory using dummy memory cells In some non-volatile storage systems, a block of data memory cells is manufactured with a dummy word line at the bottom of the block, at the top of the block, and/or at other locations. By selectively programming memory cells on the dummy word line(s), the resistanc... | 05/19/2009 |
| 7535763 | Controlled boosting in non-volatile memory soft programming A soft programming pre-charge voltage provides boosting control during soft programming operations for non-volatile memory devices. A pre-charge voltage can be applied to the word lines of a block of memory cells to enable pre-charging of the channel region of a NAN... | 05/19/2009 |
| 7535271 | Locked loop circuit with clock hold function A locked loop circuit having a clock hold function. The locked loop circuit includes a select circuit, phase mixing circuit, hold signal generator and latch circuit. The select circuit selects one of a plurality of phase values in response to a select signal, and th... | 05/19/2009 |
| 7534690 | Non-volatile memory with asymmetrical doping profile Stacked gate structures for a NAND string are created on a substrate. Source implantations are performed at a first implantation angle to areas between the stacked gate structures. Drain implantations are performed at a second implantation angle to areas between the... | 05/19/2009 |
| 7506113 | Method for configuring compensation Shifts in the apparent charge stored on a floating gate (or other charge storing element) of a non-volatile memory cell can occur because of the coupling of an electric field based on the charge stored in adjacent floating gates (or other adjacent charge storing ele... | 03/17/2009 |
| 7504686 | Self-aligned non-volatile memory cell Floating gate structures are disclosed that have a projection that extends away from the surface of a substrate. This projection may provide the floating gate with increased surface area for coupling the floating gate and the control gate. In one embodiment, the wor... | 03/17/2009 |
| 7499355 | High bandwidth one time field-programmable memory A one-time field programmable (OTP) memory cell with related manufacturing and programming techniques is disclosed. An OTP memory cell in accordance with one embodiment includes at least one resistance change element in series with a steering element. The memory cel... | 03/03/2009 |
| 7499326 | Apparatus for reducing the impact of program disturb The unintentional programming of an unselected (or inhibited) non-volatile storage element during a program operation that intends to program another non-volatile storage element is referred to as “program disturb.” A system is proposed for programming and/or re... | 03/03/2009 |
| 7499317 | System for partitioned erase and erase verification in a non-volatile memory to compensate for capacitive coupling A set of memory cells can be erased by individually erasing portions of the set in order to normalize the erase behavior of each memory cell and provide more consistent erase rates. An erase voltage pulse can be applied to the set of memory cells with a first group ... | 03/03/2009 |
| 7499150 | Distance measurement device Technology is disclosed for measuring distances. A measurement device emits a beam that reflects on the surface of an object. The measurement device determines the distance to the object, based on the time of flight of the beam from transmission to capture by the me... | 03/03/2009 |
| 7497370 | Supply chain visibility solution architecture A supply chain (or other process) visibility solution combines RFID technology with a data visibility architecture to provide real-time or near real-time supply chain information at various stages of the supply chain (or other process). The system uses a data gather... | 03/03/2009 |
| 7496896 | Accessing return values and exceptions One or more new methods are added to existing object code. The existing object code includes a first method that is capable of producing a result. New code is added to the first method. The new code provides the result to one or more of the new methods. After the mo... | 02/24/2009 |
| 7495962 | Alternating read mode Shifts in the apparent charge stored on a floating gate (or other charge storage element) of a non-volatile memory cell can occur because of the coupling of an electric field based on the charge stored in adjacent floating gates (or other charge storing elements). T... | 02/24/2009 |
| 7495956 | Reducing read disturb for non-volatile storage A system is disclosed for reducing or removing a form of read disturb in a non-volatile storage device. One embodiment seeks to prevent read disturb by eliminating or minimizing boosting of the channel of the memory elements. For example, one implementation prevents... | 02/24/2009 |
| 7495954 | Method for partitioned erase and erase verification to compensate for capacitive coupling effects in non-volatile memory A set of memory cells can be erased by individually erasing portions of the set in order to normalize the erase behavior of each memory cell and provide more consistent erase rates. An erase voltage pulse can be applied to the set of memory cells with a first group ... | 02/24/2009 |
| 7495953 | System for configuring compensation Shifts in the apparent charge stored on a floating gate (or other charge storing element) of a non-volatile memory cell can occur because of the coupling of an electric field based on the charge stored in adjacent floating gates (or other adjacent charge storing ele... | 02/24/2009 |
| 7495947 | Reverse bias trim operations in non-volatile memory A reverse bias trim operation for the reset state of a non-volatile memory system is disclosed. Non-volatile memory cells including a resistance change element undergo a reverse bias reset operation to change their resistance from a set state at a first level of res... | 02/24/2009 |
| 7495294 | Flash devices with shared word lines Word lines of a NAND flash memory array are formed by concentric, rectangular shaped, closed loops that have a width of approximately half the minimum feature size of the patterning process used. The resulting circuits have word lines linked together so that periphe... | 02/24/2009 |
| 7495282 | NAND memory with virtual channel A string of nonvolatile memory cells are connected together by source/drain regions that include an inversion layer created by fixed charge in an overlying layer. Control gates extend between floating gates so that two control gates couple to a floating gate. A fixe... | 02/24/2009 |
| 7495255 | Test pads on flash memory cards A semiconductor package is disclosed including test pads formed of solder bumps affixed to the semiconductor package during fabrication. When the package is encapsulated, due to the pressure exerted on the package during the encapsulation process, portions of the so... | 02/24/2009 |
| 7494870 | Methods of forming NAND memory with virtual channel A string of nonvolatile memory cells are connected together by source/drain regions that include an inversion layer created by fixed charge in an overlying layer. Control gates extend between floating gates so that two control gates couple to a floating gate. A fixe... | 02/24/2009 |
| 7494860 | Methods of forming nonvolatile memories with L-shaped floating gates In a nonvolatile memory using floating gates to store charge, individual floating gates are L-shaped. Orientations of L-shaped floating gates may alternate in the bit line direction and may also alternate in the word line direction. L-shaped floating gates are forme... | 02/24/2009 |
| 7492630 | Systems for reverse bias trim operations in non-volatile memory A reverse bias trim operation for the reset state of a non-volatile memory system is disclosed. Non-volatile memory cells including a resistance change element undergo a reverse bias reset operation to change their resistance from a set state at a first level of res... | 02/17/2009 |
| 7492634 | Method for programming of multi-state non-volatile memory using smart verify In a non-volatile memory, the initiation of program verification is adaptively set so that programming time is decreased. In one approach, non-volatile storage elements are programmed based on a lower page of data to have a voltage threshold (VTH) that fa... | 02/17/2009 |
| 7492363 | Telestrator system A telestrator system is disclosed that allows a broadcaster to annotate video during or after an event. For example, while televising a sporting event, an announcer (or other user) can use the present invention to draw over the video of the event to highlight one or... | 02/17/2009 |
| 7492633 | System for increasing programming speed for non-volatile memory by applying counter-transitioning waveforms to word lines Non-volatile storage elements are programmed using counter-transitioning waveform portions on neighboring word lines which reduce capacitive coupling to a selected word line. In one approach, the waveform portions extend between pass or isolation voltages of a boost... | 02/17/2009 |
| 7489549 | System for non-real time reprogramming of non-volatile memory to achieve tighter distribution of threshold voltages A set of non-volatile storage elements undergoes initial programming, after which a reprogramming, with higher verify levels, is performed in non-real time, such as when a control enters a standby mode, when no other read or write tasks are pending. The reprogrammin... | 02/10/2009 |
| 7489554 | Method for current sensing with biasing of source and P-well in non-volatile storage Current sensing is performed in a non-volatile storage device for a non-volatile storage element. A voltage is applied to a selected word line of the first non-volatile storage element, and source and p-well voltages are applied to a source and a p-well, respectivel... | 02/10/2009 |
| 7488620 | Method of fabricating leadframe based flash memory cards including singulation by straight line cuts Methods for forming leadframe-based semiconductor packages having curvilinear shapes are disclosed. The leadframes may each include one or more curvilinear slots corresponding to curvilinear edges in the finished and singulated semiconductor package. After encapsula... | 02/10/2009 |
| 7486564 | Soft programming non-volatile memory utilizing individual verification and additional soft programming of subsets of memory cells A set of non-volatile storage elements is divided into subsets for soft programming in order to more fully soft-program slower soft programming elements. The entire set of elements is soft-programmed until verified as soft programmed (or until a first subset of elem... | 02/03/2009 |
| 7487214 | Integrated electronic mail and instant messaging application An application providing a common interface allowing access and login to a electronic mail system and instant messaging system. The application allows responding to an email using an instant message, replying to an instant message using an email, sending and receivi... | 02/03/2009 |
| 7485501 | Method of manufacturing flash memory cards A method is disclosed for forming semiconductor packages by a process of punching and cutting the packages from a panel of integrated circuits. During an encapsulation process for encapsulating the packages in a molding compound, portions of the panel may be left fr... | 02/03/2009 |
| 7486561 | Method for non-real time reprogramming of non-volatile memory to achieve tighter distribution of threshold voltages A set of non-volatile storage elements undergoes initial programming, after which a reprogramming, with higher verify levels, is performed in non-real time, such as when a control enters a standby mode, when no other read or write tasks are pending. The reprogrammin... | 02/03/2009 |
| 7482223 | Multi-thickness dielectric for semiconductor memory A process provides a gate dielectric layer of a first thickness for a memory array and for certain peripheral circuits on the same substrate as the memory array. High-voltage peripheral circuits are provided with a gate dielectric layer of a second thickness. Low-vo... | 01/27/2009 |
| 7480179 | System that compensates for coupling during programming Shifts in the apparent charge stored on a floating gate (or other charge storing element) of a non-volatile memory cell can occur because of the coupling of an electric field based on the charge stored in adjacent floating gates (or other adjacent charge storing ele... | 01/20/2009 |
| 7480176 | Systems for programming differently sized margins and sensing with compensations at select states for improved read operations in non-volatile memory Non-volatile memory read operations compensate for floating gate coupling when the apparent threshold voltage of a memory cell may have shifted. A memory cell of interest can be read using a reference value based on a level of charge read from a neighboring memory c... | 01/20/2009 |
| 7478565 | Method & apparatus for fluid flow rate and density measurement A fluid flow rate and density measuring apparatus is disclosed including a section of cylindrical conduit comprising a measurement section or housing for the flow sensor. The flow sensor housing is fixedly attached to a conduit at its distal ends allowing fluid to p... | 01/20/2009 |
| 7477545 | Systems for programmable chip enable and chip address in semiconductor memory Memory die are provided with programmable chip enable circuitry to allow particular memory die to be disabled after packaging and/or programmable chip address circuitry to allow particular memory die to be readdressed after being packaged. In a multi-chip memory pac... | 01/13/2009 |
| 7478181 | Memory system and device with serialized data transfer A memory system with serialized data transfer. The memory system includes within a memory controller and a plurality of memory devices. The memory controller receives a plurality of write data values from a host and outputs the write data values as respective serial... | 01/13/2009 |
