Bizarre Patents
A hand wearable body squeegee comprising a glove portion, a concave squeegee band, and a linear squeegee band.
PatentStorm News
Make the Most of Our Site
See this month's Top Inventors and Most Cited Patents.
Stay on top of the latest innovations by subscribing to an RSS feed.
Registered users: Manage your profile.
| Number | Title | Issue Date |
| 8169077 | Dielectric interconnect structures and methods for forming the same Dielectric interconnect structures and methods for forming the same are provided. Specifically, the present invention provides a dielectric interconnect structure having a noble metal layer (e.g., Ru, Ir, Rh, Pt, RuTa, and alloys of Ru, Ir, Rh, Pt, and RuTa) that is... | 05/01/2012 |
| 8166368 | Writing a special symbol to a memory to indicate the absence of a data signal A method for writing in a memory system that includes receiving an address corresponding to a memory location in a memory, receiving a desired content to be written, encoding the desired content into a symbol, and writing the symbol to the memory location using an i... | 04/24/2012 |
| 8125809 | Adjustable write bins for multi-level analog memories An analog memory having adjustable write bins including a system for writing to the memory. The system includes a write apparatus interpreting one or more write control signals, generating a write signal, and applying the write signal at a selected memory location t... | 02/28/2012 |
| 8107276 | Resistive memory devices having a not-and (NAND) structure Resistive memories having a not-and (NAND) structure including a resistive memory cell. The resistive memory cell includes a resistive memory element for storing a resistance value and a memory element access device for controlling access to the resistive memory ele... | 01/31/2012 |
| 8105936 | Methods for forming dielectric interconnect structures Solutions for forming dielectric interconnect structures are provided. Specifically, the present invention provides methods of forming a dielectric interconnect structure having a noble metal layer that is formed directly on a modified dielectric surface. In a typic... | 01/31/2012 |
| 8037284 | Stream processing in optically linked super node clusters of processors by mapping stream graph to nodes and links A stream processing computer architecture includes creating a stream computer processing (SCP) system by forming a super node cluster of processors representing physical computation nodes (“nodes”), communicatively coupling the processors via a local interconnec... | 10/11/2011 |
| 8023345 | Iteratively writing contents to memory locations using a statistical model Systems, methods, and devices for iteratively writing contents to memory locations are provided. A statistical model is used to determine a sequence of pulses to write desired contents to a memory location. The contents can be expressed as a resistance value in a ra... | 09/20/2011 |
| 8023159 | Marking images of text with speckle patterns for theft deterrence The present invention provides methods and apparatus for embedding an identifying pattern of visible speckles into the digitized image of each page of a document. A speckle is a cluster of black or white pixels. Speckles are printed as black speckles on the white pa... | 09/20/2011 |
| 8010921 | System and method for statistical timing analysis of digital circuits The present invention is a system and method for statistical or probabilistic static timing analysis of digital circuits, taking into account statistical delay variations. The delay of each gate or wire is assumed to consist of a nominal portion, a correlated random... | 08/30/2011 |
| 8005935 | Methods and computer program products for managing application performance on a network Managing application performance on a network. A network graph is generated from a set of application endpoints on the network. The network graph is annotated by associating one or more of the application endpoints with at least one of a corresponding latency annota... | 08/23/2011 |
| 7930669 | Stage mitigation of interconnect variability The present invention provides a method, system and program product for mitigating effects of interconnect variability during a design stage of a chip. Under the technique of the present invention, a global and detailed routing of interconnects of the chip are deter... | 04/19/2011 |
| 7929338 | Memory reading method for resistance drift mitigation Techniques for reading phase change memory that mitigate resistance drift. One contemplated method includes apply a plurality of electrical input signals to the memory cell. The method includes measuring a plurality of electrical output signals from the memory cell ... | 04/19/2011 |
| 7881089 | Coding techniques for improving the sense margin in content addressable memories A content addressable memory using encoded data words and search words, and techniques for operating such device. In one embodiment, the data word is transformed into a code word guaranteeing a mismatch of at least two code word bits of different binary values durin... | 02/01/2011 |
| 7870531 | System for using partitioned masks to build a chip A mask reuse methodology process in which the soft logic is implemented with a generic array type cell structure mask and a custom blocking mask. A system is provided comprising a mask set having a plurality of reusable masks corresponding to a plurality of hard int... | 01/11/2011 |
| 7856544 | Stream processing in super node clusters of processors assigned with stream computation graph kernels and coupled by stream traffic optical links A method for implementing a stream processing computer architecture includes creating a stream computer processing (SCP) system by forming a super node cluster of processors representing physical computation nodes (“nodes”), communicatively coupling the processo... | 12/21/2010 |
| 7823795 | Pattern based elaboration of hierarchical L3GO designs A system, method and program product that utilizes flat pattern based L3GO elaboration in a hierarchical environment to create a nested conventional layout. A system is provide for processing a glyph layout to generate shapes for use in a VLSI (very large scale inte... | 11/02/2010 |
| 7823094 | Pseudo-string based pattern recognition in L3GO designs A system and method for processing glyph-based data associated with generating very large scale integrated circuit (VLSI) designs. A system is provide that includes a serialization system for converting an input region of glyph design data into a pseudo-string; and ... | 10/26/2010 |
| 7814443 | Graph-based pattern matching in L3GO designs A system and method for processing glyph-based data associated with generating very large scale integrated circuit (VLSI) designs. A system is provide that includes a system for defining variable patterns using a pattern description language to create a glyph layout... | 10/12/2010 |
| 7809821 | Trust evaluation A solution for evaluating trust in a computer infrastructure is provided. In particular, a plurality of computing devices in the computer infrastructure evaluate one or more other computing devices in the computer infrastructure based on a set of device measurements... | 10/05/2010 |
| 7805658 | DRAM Cache with on-demand reload Embodiments include a DRAM cache structure, associated circuits and method of operations suitable for use with high-speed caches. The DRAM caches do not require regular refresh of its data and hence the refresh blank-out period and refresh power are eliminated, thus... | 09/28/2010 |
| 7804710 | Multi-layer magnetic random access memory using spin-torque magnetic tunnel junctions and method for write state of the multi-layer magnetic random access memory A stacked magnetic tunnel junction (MTJ) structure of a multi-layer magnetic random access memory (MRAM) which includes a plurality of stacked MTJ devices serially connected to each other and an access transistor shared between the stacked MTJ devices. The stacked M... | 09/28/2010 |
| 7792263 | Method, system, and computer program product for displaying images of conference call participants The present invention provides a method, system, and computer program product for displaying images of conference call participants. A method in accordance with an embodiment of the present invention includes receiving a call from a user to join a conference call, o... | 09/07/2010 |
| 7737969 | System and program product for re-meshing of a three-dimensional input model using progressive implicit approximating levels A system and program product for re-meshing of a three-dimensional (3D) input model using progressive implicit approximating levels are provided. Specifically, an initial quadrilateral mesh for a 3D input model is provided. Then, an implicit approximating field is b... | 06/15/2010 |
| 7727888 | Interconnect structure and method for forming the same An interconnect structure and a method for forming the same are described. Specifically, under the present invention, a gouge is created within a via formed in the interconnect structure before any trenches are formed. This prevents the above-mentioned trench damage... | 06/01/2010 |
| 7694320 | Summary frames in video According to the invention, channel surfers are aided by summary frames appearing on the screen along with the regular program. These summary frames are embedded in the broadcast and appear in a small window on the screen at some point in the future as the video is ... | 04/06/2010 |
| 7694112 | Multiplexing output from second execution unit add/saturation processing portion of wider width intermediate result of first primitive execution unit for compound computation A method for executing multiple computational primitives is provided in accordance with exemplary embodiments. A first computational unit and at least a second computational unit cooperate to execute multiple computational primitives. The first computational unit in... | 04/06/2010 |
| 7689537 | Method, system, and computer program product for enhancing collaboration using a corporate social network The present invention provides a method, system, and computer program product for enhancing collaboration using a corporate social network to infer contacts. A method in accordance with an embodiment of the present invention includes: providing a social network for ... | 03/30/2010 |
| 7681628 | Dynamic control of back gate bias in a FinFET SRAM cell The present invention provides dynamic control of back gate bias on pull-up pFETs in a FinFET SRAM cell. A method according to the present invention includes providing a bias voltage to a back gate of at least one transistor in the SRAM cell, and dynamically control... | 03/23/2010 |
| 7539315 | Encrypted communication system, key delivery server thereof, terminal device and key sharing method Provided is a method for updating a group key in a highly secure manner and at high speed. A method includes: a step of making subscriber terminals (20) perform a part of decryption of an encrypted group key used to decrypt the information before distribution... | 05/26/2009 |
| 7519777 | Methods, systems and computer program products for concomitant pair prefetching Methods, systems and computer program products for concomitant pair per-fetching. Exemplary embodiments include a method for concomitant pair prefetching, the method including detecting a stride pattern, detecting an indirect access pattern to define an access windo... | 04/14/2009 |
| 7519526 | Charge-based circuit analysis A solution for analyzing a circuit using initial charge information is provided. In particular, one or more nodes in a design for the circuit is initialized with an initial charge. The charge can comprise a non-equilibrium charge, thereby simulating the history effe... | 04/14/2009 |
| 7516424 | Modeling and simulating a powergated hierarchical element A method, system and computer program product for modeling and simulating a powergated hierarchical element of an integrated circuit is disclosed. In modeling a powergated macro, the invention does not model all logic gates or elements as powergated, instead, the in... | 04/07/2009 |
| 7500207 | Influence-based circuit design An improved solution for designing a circuit is provided. A set of target paths, each of which has a performance attribute that is targeted for improvement, is obtained from a design for the circuit. An influence for one or more of the nodes in the set of target pat... | 03/03/2009 |
| 7480880 | Method, system, and program product for computing a yield gradient from statistical timing The invention provides a method, system, and program product for determining a gradient of a parametric yield of an integrated circuit with respect to parameters of a delay of an edge of a timing graph of the circuit. A first aspect of the invention provides a metho... | 01/20/2009 |
| 7448014 | Design stage mitigation of interconnect variability The present invention provides a method, system and program product for mitigating effects of interconnect variability during a design stage of a chip. Under the technique of the present invention, a global and detailed routing of interconnects of the chip are deter... | 11/04/2008 |
| 7443393 | Method, system, and program product for re-meshing of a three-dimensional input model using progressive implicit approximating levels A method, system and program product for re-meshing of a three-dimensional (3D)input model using progressive implicit approximating levels are provided. Specifically, an initial quadrilateral mesh for a 3D input model is provided. Then, an implicit approximating fie... | 10/28/2008 |
| 7437697 | System and method of criticality prediction in statistical timing analysis A method for determining criticality probability of an edge of a timing graph of a circuit is described. The method includes forming a directed acyclic timing graph corresponding to a circuit being timed, performing statistical timing of the circuit, for each edge o... | 10/14/2008 |
| 7435674 | Dielectric interconnect structures and methods for forming the same Dielectric interconnect structures and methods for forming the same are provided. Specifically, the present invention provides a dielectric interconnect structure having a noble metal layer (e.g., Ru, Ir, Rh, Pt, RuTa, and alloys of Ru, Ir, Rh, Pt, and RuTa) that is... | 10/14/2008 |
| 7428716 | System and method for statistical timing analysis of digital circuits The present invention is a system and method for statistical or probabilistic static timing analysis of digital circuits, taking into account statistical delay variations. The delay of each gate or wire is assumed to consist of a nominal portion, a correlated random... | 09/23/2008 |
| 7390730 | Method of fabricating a body capacitor for SOI memory A semiconductor structure having a body capacitance plate, which is formed with a process that assures that the body capacitance plate is self-aligned to both the source line (SL) diffusion and the bitline diffusion is provided. Thus the amount of overlap between th... | 06/24/2008 |
