Did You Know...
...that several people are credited with the invention of the flush toilet? Most people have heard of Thomas Crapper (1837-1910), the sanitary engineer who invented the valve-and-siphon arrangement that made the modern toilet possible. Another claimant to "the throne" was British inventor Alexander Cumming who patented a toilet in 1775. Then there's a nameless Minoan (a native of ancient Crete) who lived 4,000 years ago who supposedly was ahead of his time and created the first flush toilet!
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| Number | Title | Issue Date |
| 8185725 | Selective powering of a BHT in a processor having variable length instructions In a processor executing instructions in at least a first instruction set execution mode having a first minimum instruction length and a second instruction set execution mode having a smaller, second minimum instruction length, line and counter index addresses are f... | 05/22/2012 |
| 8185721 | Dual function adder for computing a hardware prefetch address and an arithmetic operation value A system including a dual function adder is described. In one embodiment, the system includes an adder. The adder is configured for a first instruction to determine an address for a hardware prefetch if the first instruction is a hardware prefetch instruction. The a... | 05/22/2012 |
| 8184615 | Wireless terminal methods and apparatus for establishing connections Methods and apparatus for establishing communication links, used to support communications sessions with one or more end nodes, e.g., mobile devices, are described. Various features are directed to a mobile node controlling the establishment of initial links to a fi... | 05/22/2012 |
| 8184414 | Method and apparatus for forming I/O clusters in integrated circuits A first I/O pad has a first type transistor disposed at a first end of the first I/O pad. A second I/O pad has another first type transistor disposed at a first end of the second I/O pad. The first end of the first I/O pad abuts the first end of the second I/O pad, ... | 05/22/2012 |
| 8183713 | System and method of providing power using switching circuits In a particular illustrative embodiment, a system is disclosed that includes a first power domain that is responsive to a first power switching circuit and a second power domain that is responsive to a second power switching circuit. The system also includes a logic... | 05/22/2012 |
| 8175532 | Apparatus and method for wireless communication via at least one of directional and omni-direction antennas Techniques for using at least one of omni-directional and directional antennas for communication are described. A station may be equipped antenna elements selectable for use as an omni-directional antenna or one or more directional antennas. The station may select t... | 05/08/2012 |
| 8171211 | Method and system for minimizing impact of refresh operations on volatile memory performance A memory system is provided. The system includes a volatile memory, a refresh counter configured to monitor a number of advanced refreshes performed in the volatile memory, and a controller configured to check the refresh counter to determine whether a regularly sch... | 05/01/2012 |
| 8169977 | Methods and apparatus for characterizing noise in a wireless communications system Improved pilot signal sequences which facilitate multiple channel quality measurements, e.g., through the use of different signal pilot transmission power levels, are described. In various implementations the transmitted pilot sequences facilitate determining the co... | 05/01/2012 |
| 8165203 | Line-based video rate control A method for line-based video rate control is provided. The line based video rate control method includes system feedback to change system operating parameters, including on a packet-by-packet basis and also on a line-by-line basis. Also provided is a method for lin... | 04/24/2012 |
| 8165148 | System and method for rate assignment A system and method for a time-scalable priority-based scheduler. A flexible scheduling algorithm utilizing variable scheduling durations enables better system capacity utilization. A rate request is transmitted if data arrives in a buffer, data in the buffer exceed... | 04/24/2012 |
| 8165124 | Message compression methods and apparatus Methods and apparatus for compressing messages used to support mobile communications are described. After transmission of a first mobile IP message which may be a conventional mobile IP message, a compressed mobile IP message is transmitted. The compressed message i... | 04/24/2012 |
| 8161446 | System and method of connecting a macro cell to a system power supply A system and method of connecting a macro cell to a system power supply network is disclosed. In a particular embodiment, the method includes determining a distance of an edge of the macro cell from a power line or a ground line of the system power supply network. T... | 04/17/2012 |
| 8161430 | System and method of resistance based memory circuit parameter adjustment Systems and methods of resistance based memory circuit parameter adjustment are disclosed. In a particular embodiment, a method of determining a set of parameters of a resistance based memory circuit includes selecting a first parameter based on a first predetermine... | 04/17/2012 |
| 8159888 | Recalibration systems and techniques for electronic memory applications A memory circuit includes a delay module receiving a strobe signal and producing a delayed strobe signal therefrom. The memory circuit also includes a calibration module that initiates recalibration of the delay module when the calibration module discerns that the d... | 04/17/2012 |
| 8159870 | Array structural design of magnetoresistive random access memory (MRAM) bit cells Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) bit cells are disclosed. The bit cells include a source line formed in a first plane and a bit line formed in a second plane. The bit line has a longitudinal axis that is parallel to a longitudina... | 04/17/2012 |
| 8159864 | Data integrity preservation in spin transfer torque magnetoresistive random access memory Systems, circuits and methods for controlling the word line voltage applied to word line transistors in Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) are disclosed. One embodiment is directed to a STT-MRAM including a bit cell having a magnet... | 04/17/2012 |
| 8159009 | Semiconductor device having strain material A semiconductor device having strain material is disclosed. In a particular embodiment, the semiconductor device includes a first cell including a first gate between a first drain and a first source. The semiconductor device also includes a second cell adjacent to t... | 04/17/2012 |
| 8154903 | Split path sensing circuit A sensing circuit is disclosed. The sensing circuit includes a first path including a first resistive memory device and a second path including a reference resistive memory device. The first path is coupled to a first split path including a first load transistor and... | 04/10/2012 |
| 8154900 | Method and apparatus for reducing power consumption in a content addressable memory Power consumption in a Content Addressable Memory (CAM) circuit is reduced by use of a CAM circuit. According to one embodiment of the CAM circuit, the CAM circuit includes a plurality of match lines and match line restoration circuitry. The match line restoration c... | 04/10/2012 |
| 8151266 | Operating system fast run command A fast sub-process is provided in an operating system for a digital signal processor (DSP). The fast sub-process executes a sub-process without a kernel first determining whether the sub-process resides in an internal memory, as long as certain conditions have been ... | 04/03/2012 |
| 8145883 | Preloading instructions from an instruction set other than a currently executing instruction set A preload instruction in a first instruction set is executed at a processor. The preload instruction causes the processor to preload one or more instructions into an instruction cache. The pre-loaded instructions are pre-decoded according to a second instruction set... | 03/27/2012 |
| 8145874 | System and method of data forwarding within an execution unit In an embodiment, a method is disclosed that includes, comparing, during a write back stage at an execution unit, a write identifier associated with a result to be written to a register file from execution of a first instruction to a read identifier associated with ... | 03/27/2012 |
| 8144658 | Method and apparatus for mitigating interference in a wireless communication system Techniques to mitigate inter-cell interference using joint time and frequency division are described. A frequency band is divided into multiple non-overlapping frequency subbands. The transmission timeline is divided into Tin and Tout time inte... | 03/27/2012 |
| 8144572 | Detection and mitigation of interference and jammers in an OFDM system The present invention provides a method and apparatus for detecting interference in a wireless communications system. The invention compares the receiver FFT output of a received signal against known sequences such as the packet synchronization sequence, frame synch... | 03/27/2012 |
| 8144509 | Write operation for spin transfer torque magnetoresistive random access memory with reduced bit cell size Systems, circuits and methods for controlling write operations in Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) are disclosed. A reduced bit cell size is achieved by arranging the source lines (SL) substantially in parallel with the word line... | 03/27/2012 |
| 8143952 | Three dimensional inductor and transformer A three dimensional on-chip inductor, transformer and radio frequency amplifier are disclosed. The radio frequency amplifier includes a pair of transformers and a transistor. The transformers include at least two inductively coupled inductors. The inductors include ... | 03/27/2012 |
| 8143749 | Dual current switch detection circuit with selective activation A dual current switch detection circuit with selective activation is disclosed. In a particular embodiment, the switch detection circuit comprises an input node coupled to a switch to receive an input signal from the switch, a first current source coupled to the inp... | 03/27/2012 |
| 8140823 | Multithreaded processor with lock indicator Systems and methods including a multithreaded processor with a lock indicator are disclosed. In an embodiment, a system includes means for indicating a lock status of a shared resource in a multithreaded processor. The system includes means for automatically locking... | 03/20/2012 |
| 8138814 | High signal level compliant input/output circuits A signal driver for an interface circuit has a first stage level shifter to accept input signals and output signals at a first signal level. The signal driver also has a second stage level shifter coupled to the first stage level shifter to output signals at a secon... | 03/20/2012 |
| 8135055 | I/Q calibration of transmit and receive paths in OFDM FDD communication systems I/Q gain and phase mismatches of both transmit and receive paths of an OFDM FDD transceiver are simultaneously estimated. An up-converted RF signal is generated when the transmit path performs IQ modulation on a reference signal having a single sideband tone. The up... | 03/13/2012 |
| 8134931 | Apparatus and method of generating and maintaining orthogonal connection identifications (CIDs) for wireless networks A first device is configured to select and utilize a connection identifier (CID) for a peer-to-peer communication connection between the first device and a second device in a wireless communications network. The CID is selected from a predetermined set of a pluralit... | 03/13/2012 |
| 8134856 | Data protection scheme during power-up in spin transfer torque magnetoresistive random access memory A Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) array including a plurality of bit cells, a power-up controller, and a first plurality of precharge transistors is disclosed. The plurality of bit cells are each coupled to one of a plurality of... | 03/13/2012 |
| 8130958 | Transmit power control for wireless security The present invention provides a method for establishing a secure channel between wireless devices. The method involves reducing the transmit power of the devices in conjunction with placing the devices in close proximity to one another. By reducing the transmit pow... | 03/06/2012 |
| 8130535 | Flexible word-line pulsing for STT-MRAM A method for generating a variable pulse width signal on an integrated circuit (IC) chip, includes receiving a first clock signal on the IC chip and receiving a second clock signal on the IC chip having a variable delay relative to the first clock signal. A signal h... | 03/06/2012 |
| 8130534 | System and method to read and write data a magnetic tunnel junction element A system and method to read and write data in magnetic random access memories are disclosed. In a particular embodiment, a device includes a spin transfer torque magnetic tunnel junction (STT-MTJ) element and a transistor with a first gate and a second gate coupled ... | 03/06/2012 |
| 8127184 | System and method including built-in self test (BIST) circuit to test cache memory A resizable cache memory and a system including a Built-In Self Test (BIST) circuit configured to test a cache memory are disclosed. The system further includes a non-volatile storage device including an E-fuse array to store one or more indicators. Each indicator i... | 02/28/2012 |
| 8127117 | Method and system to combine corresponding half word units from multiple register units within a microprocessor A method and system to combine corresponding half word units from multiple register units within a microprocessor, such as, for example, a digital signal processor, during execution of a single instruction are described. An instruction to combine predetermined dispa... | 02/28/2012 |
| 8127114 | System and method for executing instructions prior to an execution stage in a processor A method of processing a plurality of instructions in multiple pipeline stages within a pipeline processor is disclosed. The method partially or wholly executes a stalled instruction in a pipeline stage that has a function other than instruction execution prior to t... | 02/28/2012 |
| 8125040 | Two mask MTJ integration for STT MRAM A method for forming a magnetic tunnel junction (MTJ) for magnetic random access memory (MRAM) using two masks includes depositing over an interlevel dielectric layer containing an exposed first interconnect metallization, a first electrode, a fixed magnetization la... | 02/28/2012 |
| 8122231 | Software selectable adjustment of SIMD parallelism Selective power control of one or more processing elements matches a degree of parallelism to requirements of a task performed in a highly parallel programmable data processor. For example, when program operations require less than the full width of the data path, a... | 02/21/2012 |
