Did You Know...
...that a workman who left the soap mixing machine on too long was responsible for making Ivory Soap? He was so embarrassed by his mistake that he threw the mess in a stream. Imagine his dismay when the evidence of his error floated to the surface! Result: Ivory soap, the soap that floats.
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| Number | Title | Issue Date |
| 8081043 | Method and apparatus for varying an impedance A method and apparatus for dynamically varying the impedance of a tank circuit whereby, over time, the response of the circuit to a received signal is maximized. ... | 12/20/2011 |
| 7636397 | Method and apparatus for transmitting and receiving convolutionally coded data for use with combined binary phase shift keying (BPSK) modulation and pulse position modulation (PPM) A method and apparatus for transmitting and receiving convolutionally coded data in a communication system employing a combination of Pulse Position Modulation (PPM) and Binary Phase Shift Keying (BPSK), wherein the code is selected to have error rate performance th... | 12/22/2009 |
| 7586385 | Method and apparatus for varying an impedance A method and apparatus for dynamically varying the impedance of a tank circuit whereby, over time, the response of the circuit to a received signal is maximized. ... | 09/08/2009 |
| 7155465 | Method and apparatus for automatically archiving a file system In a digital data processing system having an on-line file system component, a method and apparatus for archiving the contents of a selected client volume stored on the file system. The archiving is performed automatically, beginning with an initial duplication of t... | 12/26/2006 |
| 7152240 | Method for communication security and apparatus therefor A FireNet security system in which trustworthy networks, called BlackNets, each comprising One (1) or more client computers, are protected by FireBreaks against attacks from untrustworthy networks, called RedNets. All incoming transactions from the RedNet are examin... | 12/19/2006 |
| 6646941 | Apparatus for operating an integrated circuit having a sleep mode An apparatus for operating a dynamic memory (11) in a sleep mode. The apparatus writes a predetermined background value to at least a background portion of the memory, and then ceases to refresh the background portion. The background value corresponds to ... | 11/11/2003 |
| 5021991 | Coprocessor instruction format A system for interfacing a Processor to a Coprocessor using standard bus cycles. The Processor, upon encountering in its instruction stream an instruction having a particular Operation word format, will transfer a Command word following the Operation word... | 06/04/1991 |
| 4890223 | Paged memory management unit which evaluates access permissions when creating translator A paged memory management unit (PMMU) adapted to translate each of a plurality of logical addresses into a corresponding physical address using a selected one of a plurality of descriptors comprising one or more translation tables stored in a memory, the ... | 12/26/1989 |
| 4821231 | Method and apparatus for selectively evaluating an effective address for a coprocessor A system for interfacing a Processor to a Coprocessor using standard bus cycles. The Processor, upon encountering in its instruction stream an instruction having a particular Operation word format, will transfer a Command word following the Operation word... | 04/11/1989 |
| 4811274 | Method and apparatus for selectively evaluating an effective address for a coprocessor A system for interfacing a Processor to a Coprocessor using standard bus cycles. The Processor, upon encountering in its instruction stream an instruction having a particular Operation word format, will transfer a Command word following the Operation word... | 03/07/1989 |
| 4802089 | Status flag handling in a digital data processing system Status flag handling method and apparatus for use in a digital data processing system provide error-resistant operation and simplicity. Two storage elements comprising one bit of a status register are operated such that: a reset places both elements in fi... | 01/31/1989 |
| 4802086 | FINUFO cache replacement method and apparatus A cache location selector selects locations in a cache for loading new information using either a valid chain, if not all locations already contain valid information, or a history loop otherwise. The valid chain selects the "highest" location in the cache... | 01/31/1989 |
| 4800489 | Paged memory management unit capable of selectively supporting multiple address spaces A paged memory management unit (PMMU) adapted to selectively access a plurality of pointer tables and page tables stored in a memory to translate a selected logical address into a corresponding physical address by first combining a first portion of the lo... | 01/24/1989 |
| 4799199 | Bus master having burst transfer mode A data processing system having a bus master and a memory which is capable of transferring operands in bursts of m in response to a burst request signal provided by the bus master, the operands being clustered modulo m about a selected access address prov... | 01/17/1989 |
| 4796235 | Write protect mechanism for non-volatile memory A write protect mechanism for a programmable read-only memory prevents writes to the PROM unless a protect register contains predetermined information. The protect register is itself a write protected control register. The predetermined information cannot... | 01/03/1989 |
| 4794434 | Trench cell for a dram A DRAM memory cell has a trench capacitor and a transistor. The trench of the trench capacitor penetrates to a buried layer which acts as the primary portion of one of the plates of the capacitor. When the buried layer is the same conductivity type as the... | 12/27/1988 |
| 4794558 | Microprocessor having self-programmed eprom A single-chip microcomputer comprises a CPU (1), a RAM (2), an EPROM (3), a timer (4), serial I/O communication logic (5), four I/O ports (11-14) and an input pin for providing a RESET signal or programming potential VPP (23). An EPROM control ... | 12/27/1988 |
| 4791324 | CMOS differential-amplifier sense amplifier A CMOS sense amplifier for use in a memory comprises two CMOS differential amplifiers. Each differential amplifier receives the same two signals generated from a selected bit line pair and each provides a different one of a complementary pair of signals. ... | 12/13/1988 |
| 4791405 | Data converter for directly providing outputs in two's complement code A method for directly providing a conversion of an analog input signal to a digital signal in two's complement code with a sampled data converter. Positive and negative reference voltages and an analog ground voltage are required. After a sign bit determi... | 12/13/1988 |
| 4791075 | Process for making a hermetic low cost pin grid array package A process for making hermetic, low cost pin grid array (PGA) semiconductor die packages. The process involves die bonding a semiconductor die or integrated circuit chip to a substrate having an interconnect or metallization pattern thereon. The die is ele... | 12/13/1988 |
| 4791615 | Memory with redundancy and predecoded signals A memory has an address buffer which receives a row address and a column address and outputs these buffered address signals to a predecoder. A row decoder and column decoder use predecoded signals provided by the predecoder to select a row and a column fr... | 12/13/1988 |
| 4785258 | CMOS amplifier circuit which minimizes power supply noise coupled via a substrate A CMOS circuit having a differential input stage which provides a single output is provided. An output stage has a capacitor which is used as a Miller integrator coupled thereto for frequency stabilization. A cascode portion is coupled to the Miller integ... | 11/15/1988 |
| 4785411 | Cascade filter structure with time overlapped partial addition operations and programmable tap length A filter structure uses multiple discrete filter circuits which are cascaded to provide a multiple tap filter of programmable tap length. In one form, an FIR filter may be implemented wherein each circuit generates partial sum operands which must be added... | 11/15/1988 |
| 4782305 | Differential input-single output two pole filter implemented by a single amplifier An analog two pole filter is provided which uses a single amplifier to implement a predetermined transfer function. The filter has a differential input and converts the two inputs to a single output utilizing the same amplifier which performs the filterin... | 11/01/1988 |
| 4782326 | ADPCM transcoder data interface circuit having an encoded enable signal A data interface circuit for use when interfacing between two communication links communicating frames of digital data in PCM and ADPCM formats is provided. The data interface circuit provides control information for selecting one of a plurality of algori... | 11/01/1988 |
| 4780843 | Wait mode power reduction system and method for data processor A method and apparatus for reducing power consumption in a data processing system by interrupting the supply of clocking pulses to selected portions of the system in response to a power-down signal provided by a data processing portion of the system only ... | 10/25/1988 |
| 4777613 | Floating point numeric data processor A numeric data processor having an execution unit adapted to efficiently execute the complete set of floating point operations recommended by the IEEE Standard for Binary Floating-Point Arithmetic, ANSI/IEEE Std. 754-1985, in full compliance therewith. Th... | 10/11/1988 |
| 4775642 | Modified source/drain implants in a double-poly non-volatile memory process Implementing modified souce/drain implants in a non-volatile memory process while leaving the source/drain regions in the memory cells of the device unmodified and adding no critical mask steps. Methods for implementing both low dose drain and graded sour... | 10/04/1988 |
| 4771249 | Phase locked loop having a filter with controlled variable bandwidth A phase locked loop (PLL) is provided having a filter with a programmable wide and narrow bandwith. When PLL circuit operation is initiated or when the operational frequency of the PLL is changed by a substantial amount, a phase detector functions to forc... | 09/13/1988 |
| 4766537 | Paged memory management unit having stack change control register A paged memory management unit (PMMU) adapted to prevent unauthorized access by a calling module executing in a data processor to a called module having a higher access level. A Stack Change Control Register in the PMMU has a bit corresponding to each val... | 08/23/1988 |
| 4766531 | Method and apparatus for generating the next microaddress for a micromachine The current microinstruction of a micromachine enables a selected one of a plurality of conditions to select one of a plurality of microaddress qualifiers to be combined with a specified base microaddress to form the next microaddress for the micromachine... | 08/23/1988 |
| 4766473 | Single transistor cell for electrically-erasable programmable read-only memory and array thereof A single transistor EEPROM cell comprises a source, a channel, a drain, a floating gate and a control gate. The control gate and the floating gate are co-extensive over the channel. Programming is achieved by charge injection from the channel and erasing ... | 08/23/1988 |
| 4766561 | Method and apparatus for implementing multiple filters with shared components A structure for implementing a plurality of independent filters, such as finite impulse response filters, in an efficient manner. Coefficient and data operands associated with each of the independent filters are stored in a predetermined order in a storag... | 08/23/1988 |
| 4764900 | High speed write technique for a memory In a random access memory a write driver develops a full rail write signal which is coupled to the selected bit line pair via transmission gates. The bit lines are thus driven to full rail. This results in a faster rise time on the bit line which is drive... | 08/16/1988 |
| 4764477 | CMOS process flow with small gate geometry LDO N-channel transistors A process for forming lightly doped drains in a CMOS circuit utilizing two photoresist masks is disclosed. After gates for N-channel and P-channel transistors have been formed, an N-implant is effected. A first photoresist mask is used as a source/drain i... | 08/16/1988 |
| 4764888 | N-bit carry select adder circuit with double carry select generation A circuit for adding two N-bit binary numbers with an input carry bit, where N is an integer, by the carry select technique is provided. A ranked ordered plurality of section adders function in conjunction with rank ordered carry select logic circuits to ... | 08/16/1988 |
| 4763181 | High density non-charge-sensing DRAM cell A non-charge-sensing high density dynamic random access memory (DRAM) cell using a trench capacitor as a vertical FET and two active field effect transistors (FETs). A particular bit line is shared by the cells on either side of it; the bit line on one si... | 08/09/1988 |
| 4763306 | Circuit for enabling a transmission gate in response to predecoded signals A memory has a transmission gate requiring complementary signals for coupling a bit line to a data line. The complementary signals are generated utilizing a simplified circuit which does not require complementary predecoded signals. Two predecoded signals... | 08/09/1988 |
| 4763305 | Intelligent write in an EEPROM with data and erase check A memory provides a byte program mode which avoids unnecessary erase and program cycles. If a byte is to be programmed, the new data to be written is first compared to the existing data in the byte. If the old data is the same as the new data, there is no... | 08/09/1988 |
| 4763296 | Watchdog timer A data processor (2) including a watchdog timer (8) comprising: a first memory (4) holding a primary operating routine for cyclic execution during operation of the data processor, an address bus (6) for addressing locations in said first memory means, a t... | 08/09/1988 |
