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| Number | Title | Issue Date |
| 7113966 | Method and apparatus for decorrelating a random number generator using a pseudo-random sequence A method and apparatus are disclosed for generating random numbers using the meta-stable behavior of flip-flops. A flip-flop is clocked with an input that deliberately violates the setup or hold times (or both) of the flip-flop to ensure meta-stable behavior. When a... | 09/26/2006 |
| 7085950 | Parallel data communication realignment of data sent in multiple groups A high-speed parallel data communication approach overcomes data skewing concerns by concurrently transmitting data in a plurality of multiple-bit groups and, after receiving the concurrently-transmitted data, realigning skew-caused misalignments between the groups.... | 08/01/2006 |
| 7079061 | Sigma Delta and converter with pseudo flash converter The invention relates to a Sigma Delta A/D converter (2) for generating a N-bits digital output signal (4) on the basis of an analogue input signal (6), comprising a control loop which comprises a quantizer (8) comprising at least a compa... | 07/18/2006 |
| 7076612 | Cache interface circuit for automatic control of cache bypass modes and associated power savings A cache interface circuit includes a processor interface for receiving memory access requests from a processor, and for transmitting memory data back to the processor in response to processor requests. A main memory interface provides for issuing main memory access ... | 07/11/2006 |
| 7050967 | Speech coding system In a speech coding system with an encoder and a decoder cooperating with said encoder, the speech encoder comprises a pre-processor and an ADPCM encoder with a quantizer and step-size adaptation means, while the speech decoder comprises an ADPCM decoder with similar... | 05/23/2006 |
| 7050485 | Iterative CDMA phase and frequency acquisition A system and method is provided that searches for the frequency and phase of a CDMA transmission in an iterative manner. With its automatic frequency control (AFC) disabled, the receiving system performs a coarse search for the transmitter's CDMA phase at a nominal ... | 05/23/2006 |
| 7042378 | Circuit with a digital to analog converter A first and second signal source are coupled to an analog output in a digital input signal dependent configuration. The signal sources so that a contribution of their source signals adds up in a first or a second direction when the digital input assumes a first or a... | 05/09/2006 |
| 7038721 | Gamma correction circuit A gamma correction circuit for correcting a digital video signal, the circuit comprising first (6) and second (8) lookup tables for storing discrete output intensity data and the associated slope data of a non-linear transfer function, respectively, fo... | 05/02/2006 |
| 7038496 | Device for comparison of frequencies with low temporal inertia The present invention relates to a device for comparison CMP, which is designed to emit a control signal Vcnt, which is representative of a difference which exists between the input signal frequencies Vdiv and Vref. The device according to the invention includes a p... | 05/02/2006 |
| 7038434 | Voltage regulator A low dropout voltage regulator comprising a series-regulating element (T1) between an input (I) and an output (O) of the voltage regulator, and a differential input error amplifier (1) having a first output (O1) coupled to a control input of th... | 05/02/2006 |
| 7039113 | Selective decoding of enhanced video stream An MPEG decoding system selectively decodes MPEG enhanced streams, based on a select identification of an enhancement region of a series of image frames. MPEG blocks within the enhancement region are decoded with the enhancement-layer, while blocks outside the enhan... | 05/02/2006 |
| 7034726 | Data converter A data converter comprises a discrete-time sigma delta modulator e.g. for driving a Class-D power amplifier. The low-pass filter of the sigma delta modulator is modified by adding a suitably positioned pole to lower the oscillation frequency (limit cycle) of the sig... | 04/25/2006 |
| 7032100 | Simple algorithmic cryptography engine A processor architecture and instruction set is provided that is particularly well suited for cryptographic processing. A variety of techniques are employed to minimize the complexity of the design and to minimize the complexity of the interconnections within the de... | 04/18/2006 |
| 7024346 | Automatic ATAP test bench generator A system is provided for automatically generating ATAP test solutions. The system includes ATAP simulation circuitry, a bus, an ATAP test bench file, an output file, and a test program. The ATAP simulation circuitry is switchably coupled to a selected analog cell ha... | 04/04/2006 |
| 7016652 | Automatic frequency control receiver The invention relates to a receiver of signals [S] received from a wireless network, said receiver working at a so-called reference oscillation frequency controlled by a so-called reference value [Vref]. Said receiver includes demodulation means [DEMO] for demodulat... | 03/21/2006 |
| 6999769 | Method for in-progress telephone call transfer between a wireless telephone and a wired telephone using a short-range communication control link In-progress call transfer between a wireless telephone and a wired telephone is effected using a short-range wireless communication link between the devices. Each of the devices are provisioned to include a short-range radio or infrared transceiver so that the devic... | 02/14/2006 |
| 6999529 | Digital AM demodulator For a digital demodulator for AM demodulation of a difference sound signal in a digital multiplex signal, which multiplex signal also comprises a sum sound signal in the baseband position and a pilot carrier at a pilot frequency, and the difference sound signal is m... | 02/14/2006 |
| 6996703 | Processing device for executing virtual machine instructions A processing device comprises an instruction memory 120 for storing virtual machine instructions, such as Java byte codes. A processor 112 of the processing device comprises a predetermined microcontroller core 114 for executing native instructi... | 02/07/2006 |
| 6996759 | Delay fault test circuitry and related method The invention provides for a delay fault testing method and related circuitry for producing a test pulse in response to an input clock signal, and including analysing first and second clock signals having different frequencies and associated with logic circuits havi... | 02/07/2006 |
| 6995608 | Reconfigurable analog cell and an arrangement comprising a plurality of such cell The reconfigurable analog cell according to the invention comprises admittances yab having first terminals (a) which are coupled to first terminals SW1 of a first plurality of switches, and having second terminals which are coupled to the first ter... | 02/07/2006 |
| 6996524 | Speech enhancement device A speech enhancement system for the reduction of background noise comprises a time-to-frequency transformation unit to transform frames of time-domain samples of audio signals to the frequency domain, background noise reduction means to perform noise reduction in th... | 02/07/2006 |
| 6988230 | Test arrangement for assemblages of intergrated circuit blocks An electronic device has a plurality of subdevices with each subdevice coupled to a test interface. The test interfaces are arranged in a chain of test interfaces by coupling the TDO contact of a predecessor test interface to the TDI contact of a successor test inte... | 01/17/2006 |
| 6980049 | Polyphase-notchfilter The invention relates to a Polyphase-Notchfilter for filtering input signals comprising known bandpass filters, which comprise voltage-controlled current sources. To provide an integrated circuit that has notch filter functionality with reduced circuit erogation, th... | 12/27/2005 |
| 6978026 | Circuit arrangement for gaining a stereo subcarrier and an RDS carrier According to the invention, a circuit arrangement for gaining a 38 kHz stereo subcarrier and a 57 kHz RDS carrier for decoding a stereo signal comprised in a demodulated FM signal and/or an RDS signal comprised in a demodulated FM signal, having a simple structure w... | 12/20/2005 |
| 6963890 | Reconfigurable digital filter having multiple filtering modes A hardware-configurable digital filter is adaptable for providing multiple filtering modes. In one embodiment, the digital filter includes a register-based array of logic circuitry, computational circuitry and mode selection circuitry. By reconfiguring data flow wit... | 11/08/2005 |
| 6963625 | Dada decoding An arrangement for selecting the largest of a plurality of input currents (pma (k−1), pmb (k−1)) and adding a further current (Ibmk) to the selected current, the arrangement comprising: a plurality of inputs (901, 902) for receiving said input currents; a... | 11/08/2005 |
| 6959371 | Dynamic access control of a function to a collective resource Access by a function to a collective resource is controlled by requiring that the function waits for a minimum number of clock cycles CLK called latency [LAT] between two successive accesses of the function. The function is further required to wait a number of cycle... | 10/25/2005 |
| 6940523 | On the fly data transfer between RGB and YCrCb color spaces for DCT interface A method for transferring data on the fly between an RGB color space and a YCrCb color space useful for a DCT block-computation engine significantly increases throughput and decreases processor overhead. According to one example embodiment, data is transferred from ... | 09/06/2005 |
| 6928597 | Method and apparatus for testing digital circuitry Digital circuitry is tested through effecting a paired data loop-back from a first buffered output to a first buffered input whilst within the circuitry executing at least part of the test through using a Built-In-Self-Test methodology. In particular, the loop-back ... | 08/09/2005 |
| 6920576 | Parallel data communication having multiple sync codes A high-speed parallel-data communication approach overcomes skewing problems by transferring digital data with automatic realignment. In one example embodiment, a parallel bus has parallel bus lines adapted to transfer digital data from a data file, along with a syn... | 07/19/2005 |
| 6917365 | Processor provided with a slow-down facility through programmed stall cycles A processor executes image processing under control of a clock facility, such that a sequence of C effective clock cycles will effect a processing operation of a predetermined amount of image information. In particular, the processor has programming means for implem... | 07/12/2005 |
| 6917387 | Arrangement for time-correct combination of two data streams Methods and apparatus are described for time-correct combination of two data streams, particularly video data streams. In this case, a sync signal of the first video data stream is a horizontal sync signal. In this case, methods and apparatus are provided to combine... | 07/12/2005 |
| 6918123 | Calls identify scenario for control of software objects via property routes An information processing system has first and second physical components represented by a first and second software objects. Both objects have properties that are changeable through calls to the objects. The system enables registering a property route linking a fir... | 07/12/2005 |
| 6912615 | Control means for burst access control The invention relates to a control means for controlling burst accesses to a synchronous dynamic semiconductor memory device comprising at least two memory banks. In order to avoid relatively large time losses due to preparation cycles (precharge and activate), the ... | 06/28/2005 |
| 6911863 | Integrated DVB filter A filter for processing frequency signals, preferably received, particularly digital television signals is described, which filter comprises a Chebyshev filter (11, 12), a subsequent all-pass filter (13) and a control device (14 to 20) fo... | 06/28/2005 |
| 6910207 | Method of executing a computer program with an interpreter, computer system and computer program product An interpreter uses a symbol table containing information for resolving symbolic references in instructions. Memory is provided for storing symbolic reference-result associations, the result of the association having resulted from resolving the symbolic reference of... | 06/21/2005 |
| 6907559 | Method and apparatus for data reproduction DVD data is read from an optical disc. Double buffering is used for outer error correction syndromes, the syndrome for one ECC frame being accumulated in one syndrome buffer, while error correction calculations for preceding data block are performed using a syndrome... | 06/14/2005 |
| 6904510 | Data processor having a respective multiplexer for each particular field A data processor that can perform instructions in parallel on respective fields in an operand includes a respective multiplexer for each of the respective fields. Each respective multiplexer is controlled by condition data for a particular field, preferably from an ... | 06/07/2005 |
| 6901487 | Device for processing data by means of a plurality of processors A data processing device comprises a plurality of processors that are to access a memory system. The memory system comprises at least two memories The data processing device comprises a bus per memory. The buses are interconnected by at least one bridge. A processor... | 05/31/2005 |
| 6888852 | Signal combining circuit having two A/D converters To provide a digital signal combining circuit having a function to combine two digital signals converted from two analog signals and a function to compensate for nonlinearity of two A/D converters upon input of one analog input signal and to convert the analog input... | 05/03/2005 |
