Quotables
"This is the patent age of new inventions for killing bodies, and for saving souls. All propagated with the best intentions."
Lord Byron ;
PatentStorm News
Make the Most of Our Site
See this month's Top Inventors and Most Cited Patents.
Stay on top of the latest innovations by subscribing to an RSS feed.
Registered users: Manage your profile.
| Number | Title | Issue Date |
| 8159244 | Method and system for testing a semiconductor package A method and system for testing a semiconductor package. At least some of the illustrative embodiments are methods comprising testing a semiconductor package unit (150, 420) by electrically coupling a top printed circuit board (208, 420) to a top-side ... | 04/17/2012 |
| 8072770 | Semiconductor package with a mold material encapsulating a chip and a portion of a lead frame Various exemplary embodiments provide components, devices, and methods of semiconductor packaging. The disclosed packaging component can include a mold material disposed around a lead frame and at least an integrated circuit (IC), wherein the IC is electrically conn... | 12/06/2011 |
| 8058706 | Delamination resistant packaged die having support and shaped die having protruding lip on support A packaged electronic device includes a thickness shaped IC die including a top portion, top surface, active circuitry, bottom portion and bottom surface. A cross sectional area of the bottom surface is ≧5% less than a cross sectional area of the top surface to pr... | 11/15/2011 |
| 8053876 | Multi lead frame power package According to an embodiment of the invention, a system, operable to facilitate dissipation of thermal energy, includes a mold compound, a die, a first lead frame, and a second lead frame. The die is disposed within the mold compound, and in operation generates therma... | 11/08/2011 |
| 8053873 | IC having voltage regulated integrated Faraday shield An integrated circuit (IC) includes a substrate having a top semiconductor surface and a bottom surface, and integrated circuitry including an analog subcircuit and at least one digital subcircuit formed on the top semiconductor surface. A plurality of through subst... | 11/08/2011 |
| 8053349 | BGA package with traces for plating pads under the chip A semiconductor flip-chip ball grid array package (600) with one-metal-layered substrate. The sites (611) of a two-dimensional array become usable for attaching solder balls of the signal (non-common net assignment) I/O type to the substrate under the ... | 11/08/2011 |
| 8053285 | Thermally enhanced single inline package (SIP) In a method and system for fabricating a thermally enhanced semiconductor device (200, 300) is packaged as a through hole single inline package (SIP). A leadframe (210, 310, 410) having a die pad (220, 320, 420) to attach an IC die (230, 330 | 11/08/2011 |
| 8049320 | Integrated circuit stacked package precursors and stacked packaged devices and systems therefrom A package-on-package (POP) package precursor and packaged devices and systems therefrom includes an electronic substrate including electrically conductive layers and a top surface. A first portion of the top surface has an IC die attached thereon. A second portion o... | 11/01/2011 |
| 8049312 | Semiconductor device package and method of assembly thereof A semiconductor die package includes: an assembly including a semiconductor die, a clip structure attached to an upper surface of the semiconductor die, and a heat sink attached to an upper surface of the clip structure; and a molding material partially encapsulatin... | 11/01/2011 |
| 8049119 | Integrated circuit package having integrated faraday shield A packaged integrated circuit (IC) (100) includes a first substrate (110) comprising a first plurality of layers and a first circuit coupling features (112) at an upper surface of the first substrate (110), the first plurality of layers i... | 11/01/2011 |
| 8048358 | Pop semiconductor device manufacturing method The objective of the invention is to prevent electrostatic destruction of semiconductor chips during resin molding. With the semiconductor device manufacturing method, a substrate 400 that includes on the surface multiple semiconductor chips 410 and li... | 11/01/2011 |
| 8044495 | Metallic leadframes having laser-treated surfaces for improved adhesion to polymeric compounds A leadframe for the assembly of a semiconductor chip has regions (112) with an original smooth surface of glossy appearance and regions (113, 114, 210) of a frosty appearance with rough surface contours. The regions of rough surface contours include tw... | 10/25/2011 |
| 8043973 | Mask overhang reduction or elimination after substrate etch A method of forming IC devices includes providing a substrate and forming a patterned masking layer including at least one masked region having at least one masking layer, and a feature region bounded by the masking layer. Etching forms an etched feature in the subs... | 10/25/2011 |
| 8043545 | Methods and apparatus to evenly clamp semiconductor substrates Methods and apparatus to evenly clamp semiconductor substrates in a transfer mold process are disclosed. A disclosed split mold base includes a first plate having a first surface, a second plate having a second surface opposite the first surface, and a plurality of ... | 10/25/2011 |
| 8039956 | High current semiconductor device system having low resistance and inductance A high current semiconductor device (for example QFN for 30 to 70 A) with low resistance and low inductance is encapsulated by molding compound (401, height 402 about 0.9 mm) so that the second lead surfaces 110b remain un-encapsulated. A... | 10/18/2011 |
| 8039955 | Mold lock on heat spreader A mold lock and a method of forming the mold lock are provided. The mold lock is used in an encapsulated semiconductor device and includes a neck and a shaped head integral with the neck. The mold lock can be formed to project above a support component, such as a he... | 10/18/2011 |
| 8039385 | IC devices having TSVS including protruding tips having IMC blocking tip ends A through substrate via (TSV) die includes a plurality of TSVs including an outer dielectric sleeve and an inner metal core and protruding TSV tips including sidewalls that emerge from the TSV die. A passivation layer lateral to the protruding TSV tips is on a porti... | 10/18/2011 |
| 8039320 | Optimized circuit design layout for high performance ball grid array packages A method of laying out traces for connection of bond pads of a semiconductor chip to a printed wiring board or the like and the layout. There is provided a substrate having top and bottom surfaces with a plurality of rows and columns of vias extending therethrough f... | 10/18/2011 |
| 8039317 | Aluminum leadframes for semiconductor QFN/SON devices A post-mold plated semiconductor device has an aluminum leadframe (105) with a structure including a chip mount pad and a plurality of lead segments without cantilevered lead portions. A semiconductor chip (210) is attached to the chip mount pad, and c... | 10/18/2011 |
| 8039309 | Systems and methods for post-circuitization assembly A method of making integrated circuit packages using a conductive plate as a substrate includes forming a partial circuit pattern on one side of the conductive plate by stamping or selectively removing a portion of the conductive plate through part of its thickness,... | 10/18/2011 |
| 8034660 | PoP precursor with interposer for top package bond pad pitch compensation An electronic assembly adapted for forming package on package (PoP) devices includes a package substrate having a molded IC die thereon that defines a mold cap height and substrate contact pads lateral to the molded IC die. An interposer including an interposer subs... | 10/11/2011 |
| 8030959 | Device-under-test power management One embodiment of the present invention includes a system for managing power to a plurality of devices-under-test (DUTs). The system comprises a DUT test system configured to perform at least one test associated with operation of the DUTs and to monitor current asso... | 10/04/2011 |
| 8030137 | Flexible interposer for stacking semiconductor chips and connecting same to substrate A semiconductor device with a first (101) and a second (111) semiconductor chip assembled on an insulating flexible interposer (120). The interposer, preferably about 25 to 50 μm thick, has conductive traces (121), a central planar recta... | 10/04/2011 |
| 8017439 | Dual carrier for joining IC die or wafers to TSV wafers A method of forming stacked electronic articles using a through substrate via (TSV) wafer includes mounting a first carrier wafer to a top side of the TSV wafer using a first adhesive material that has a first debonding temperature. The TSV wafer is thinned from a b... | 09/13/2011 |
| 8017410 | Power semiconductor devices having integrated inductor An electronic device (100) with one or more semiconductor chips (102) has an inductor (101) assembled on or under the chips. The inductor includes a ferromagnetic body (111) and a wire (104) wrapped around the body to form at least... | 09/13/2011 |
| 8008183 | Dual capillary IC wirebonding The invention discloses apparatus and methods for the formation of bond wires in integrated circuit assemblies by attaching two separate wires using a dual capillary bond head. The separate wires are preferably non-identical, for example, being of different gauges a... | 08/30/2011 |
| 8008131 | Semiconductor chip package assembly method and apparatus for countering leadfinger deformation The invention provides semiconductor chip packages, tools, and methods for preventing and for correcting leadfinger deformation caused during wirebonding in semiconductor chip package manufacturing. Disclosed are improved heat blocks and methods for their use in ens... | 08/30/2011 |
| 8000921 | Method and apparatus for synchronizing signals in a testing system The preferred embodiments of the present invention provide approaches for synchronizing signals in a testing system. In some embodiments, the timing signal associated with each device under test (DUT) is maintained at an integer multiple of the tester timing signal.... | 08/16/2011 |
| 7989949 | Heat extraction from packaged semiconductor chips, scalable with chip area A semiconductor device (100A) with plastic encapsulation compound (102) and metal sheets (103a and 104) on both surfaces, acting as heat spreaders. One or more thermal conductors (103a) of preferably uniform height co... | 08/02/2011 |
| 7973416 | Thru silicon enabled die stacking scheme A die to die bonding system and method includes an upper die having a front side, a back side, and a fully filled thru silicon via, a portion of the fully filled thru silicon via protruding from the back side of the upper die. A lower die includes a front side, a ba... | 07/05/2011 |
| 7972905 | Packaged electronic device having metal comprising self-healing die attach material A method of assembling an electronic device and electronic packages therefrom. A die attach adhesive precursor is placed between a top surface of a workpiece and an IC die. The die attach adhesive precursor includes metal particles, a first plurality of first microc... | 07/05/2011 |
| 7971351 | Method of manufacturing a semiconductor device The objective of the invention is to provide a method of manufacturing a semiconductor device that allows individual molding of plural semiconductor chips carried on a surface of the substrate. It includes the following process steps: a process step in which plural ... | 07/05/2011 |
| 7960840 | Double wafer carrier process for creating integrated circuit die with through-silicon vias and micro-electro-mechanical systems protected by a hermetic cavity created at the wafer level A TSV-MEMS packaging process is provided. The process includes forming TSVs in the front side of the product wafer, and attaching a first carrier to the front side of the product wafer, subsequent to forming TSVs. The process further includes thinning the back side ... | 06/14/2011 |
| 7956456 | Thermal interface material design for enhanced thermal performance and improved package structural integrity An electronic package comprising a semiconductor device, a heat spreader layer, and a thermal interface material layer located between the semiconductor device and the heat spreader layer. The thermal interface material layer includes a resin layer having heat condu... | 06/07/2011 |
| 7956445 | Packaged integrated circuit having gold removed from a lead frame A method of packaging an integrated circuit, including providing a lead frame having lead fingers, where the lead frame has a gold layer thereon on a top surface and a bottom surface. An integrated circuit die is attached to the lead frame. The gold layer is substan... | 06/07/2011 |
| 7955041 | Quick changeover apparatus and methods for wafer handling Quick changeover apparatus for wafer handlers capable of handling at least two sizes of wafer frames and methods of using such apparatus are disclosed. ... | 06/07/2011 |
| 7947602 | Conductive pattern formation method The objective of the present invention is to offer a method for forming a conductive pattern on a substrate and solder protrusions on the conductive pattern. The pitch of the conductive pattern corresponds to the pitch of electrodes on a semiconductor chip. ... | 05/24/2011 |
| 7944034 | Array molded package-on-package having redistribution lines A semiconductor device with a sheet-like insulating substrate (101) integral with two or more patterned layers of conductive lines and vias, a chip attached to an assembly site, and contact pads (103) in pad locations has an encapsulated region on the ... | 05/17/2011 |
| 7943514 | Integrated circuits having TSVs including metal gettering dielectric liners An IC includes a substrate having a semiconductor top surface and a bottom surface, wherein the semiconductor top surface includes one or more active circuit components and a plurality of through silicon vias (TSVs) extending through the substrate. The plurality of ... | 05/17/2011 |
| 7943425 | Semiconductor wafer sawing system and method Semiconductor wafer sawing systems and methods are described in which a wafer may be secured in a sawing position having a surface exposed to incur sawing with at least a portion of the exposed wafer surface positioned below the center of gravity of the wafer such t... | 05/17/2011 |
