Did You Know...
...that the inventor of the electric motor was a blacksmith named Thomas Davenport? Described as "a brilliantly unsuccessful inventor", Davenport invented the first rotary electric motor. In 1836 he headed out -- on foot -- from his Vermont home to file a patent application at the Patent Office in Washington, D.C. By the time he got there, he had squandered away his money and couldn't afford the $30 filing fee so he turned around and went home. When he later mailed in his application with money he'd raised, the Patent office was destroyed in a fire. He did finally get credit for his invention on Feb. 5, 1837.
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| Number | Title | Issue Date |
| 7550337 | Dual gate dielectric SRAM An SRAM cell structure containing a PFET gate dielectric having a thicker effective oxide thickness (EOT) than an NFET gate dielectric and methods of manufacturing the same is provided. The PFET gate dielectric and the NFET gate dielectric may be silicon oxynitride ... | 06/23/2009 |
| 7544546 | Formation of carbon and semiconductor nanomaterials using molecular assemblies The invention is directed to a method of forming carbon nanomaterials or semiconductor nanomaterials. The method comprises providing a substrate and attaching a molecular precursor to the substrate. The molecular precursor includes a surface binding group for attach... | 06/09/2009 |
| 7539051 | Memory storage devices comprising different ferromagnetic material layers, and methods of making and using the same A memory storage device that contains alternating first and second ferromagnetic material layers is provided. Each first ferromagnetic material layer has a first layer thickness (L1) and a first critical current density (JC1), and each second f... | 05/26/2009 |
| 7534710 | Coupled quantum well devices (CQWD) containing two or more direct selective contacts and methods of making same The present invention relates to a device structure that contains two or more conducting layers, two peripheral insulating layers, one or more intermediate insulating layers, and two or more conductive contacts. The two or more conducting layers are sandwiched betwe... | 05/19/2009 |
| 7531293 | Radiation sensitive self-assembled monolayers and uses thereof The invention is directed to a radiation sensitive compound comprising a surface binding group proximate to one end of the compound for attachment to a substrate, and a metal binding group proximate to an opposite end of the compound. The metal binding group is not ... | 05/12/2009 |
| 7528067 | MOSFET structure with multiple self-aligned silicide contacts A metal oxide semiconductor field effect transistor (MOSFET) structure that includes multiple and distinct self-aligned silicide contacts and methods of fabricating the same are provided. The MOSFET structure includes at least one metal oxide semiconductor field eff... | 05/05/2009 |
| 7528056 | Low-cost strained SOI substrate for high-performance CMOS technology A cost-effective and simple method of fabricating strained semiconductor-on-insulator (SSOI) structures which avoids epitaxial growth and subsequent wafer bonding processing steps is provided. In accordance with the present invention, a strain-memorization technique... | 05/05/2009 |
| 7528050 | High performance field effect transistors on SOI substrate with stress-inducing material as buried insulator and methods The present invention provides a semiconductor structure that includes a high performance field effect transistor (FET) on a semiconductor-on-insulator (SOI) in which the insulator thereof is a stress-inducing material of a preselected geometry. Such a structure ach... | 05/05/2009 |
| 7521346 | Method of forming HfSiN metal for n-FET applications A compound metal comprising HfSiN which is a n-type metal having a workfunction of about 4.0 to about 4.5, preferably about 4.3, eV which is thermally stable on a gate stack comprising a high k dielectric and an interfacial layer. Furthermore, after annealing the st... | 04/21/2009 |
| 7521091 | Method of preparing an extended conjugated molecular assembly A method for preparing an extended conjugated molecular assembly includes applying onto a surface of a substrate a first molecular compound G1-Molecule1-G2, where G1 includes a first functional group, G2 includes a second functional group, and Molecule1 includes a c... | 04/21/2009 |
| 7517718 | Method for fabricating an inorganic nanocomposite An inorganic nanocomposite is prepared by obtaining a solution of a soluble hydrazine-based metal chalcogenide precursor; dispersing a nanoentity in the precursor solution; applying a solution of the precursor containing the nanoentity onto a substrate to produce a ... | 04/14/2009 |
| 7512908 | Method and apparatus for improving SRAM cell stability by using boosted word lines The present invention relates to methods and apparatus for improving the stability of static random access memory (SRAM) cells by using boosted word lines. Specifically, a boosted word line voltage (Vdd′) is applied to the word line of a selected SRAM cell, while ... | 03/31/2009 |
| 7507989 | Strained Si MOSFET on tensile-strained SiGe-on-insulator (SGOI) A semiconductor structure for use as a template for forming high-performance metal oxide semiconductor field effect transistor (MOSFET) devices is provided. More specifically, the present invention provides a structure that includes a SiGe-on-insulator substrate inc... | 03/24/2009 |
| 7504132 | Selective placement of carbon nanotubes on oxide surfaces The present invention provides a method for the selective placement of carbon nanotubes on a particular surface. In particular, the present invention provides a method in which self-assembled monolayers formed on an unpatterned or patterned metal oxide surface are u... | 03/17/2009 |
| 7494896 | Method of forming magnetic random access memory (MRAM) devices on thermally-sensitive substrates using laser transfer A method of forming a magnetic memory device on a substrate includes forming the memory device on a transparent substrate coated with a decomposable material layer subject to rapid heating resulting in a predetermined high pressure, transferring the memory device to... | 02/24/2009 |
| 7494841 | Solution-based deposition process for metal chalcogenides A solution of a hydrazine-based precursor of a metal chalcogenide is prepared by adding an elemental metal and an elemental chalcogen to a hydrazine compound. The precursor solution can be used to form a film. The precursor solutions can be used in preparing field-e... | 02/24/2009 |
| 7488630 | Method for preparing 2-dimensional semiconductor devices for integration in a third dimension A method which is intended to facilitate and/or simplify the process of fabricating interlayer vias by selective modification of the FEOL film stack on a transfer wafer is provided. Specifically, the present invention provides a method in which two dimensional devic... | 02/10/2009 |
| 7488656 | Removal of charged defects from metal oxide-gate stacks The present invention provides a method for removing charged defects from a material stack including a high k gate dielectric and a metal contact such that the final gate stack, which is useful in forming a pFET device, has a threshold voltage substantially within t... | 02/10/2009 |
| 7488640 | Aluminum nitride and aluminum oxide/aluminum nitride heterostructure gate dielectric stack based field effect transistors and method for forming same A structure (e.g., field effect transistor) and a method for making the structure, include a substrate having a source region, a drain region, and a channel region therebetween, an insulating layer disposed over the channel region, the insulating layer including a l... | 02/10/2009 |
| 7485537 | Method of fabricating a vertical bipolar transistor with a majority carrier accumulation layer as a subcollector for SOI BiCMOS with reduced buried oxide thickness The present invention provides a a method of fabricating bipolar junction transistors (BJTs) on selected areas of a very thin buried oxide (BOX) using a conventional silicon-on-insulator (SOI) starting wafer with a thick BOX. The reduced BOX thickness underneath the... | 02/03/2009 |
| 7485506 | Hybrid substrate technology for high-mobility planar and multiple-gate MOSFETS A hybrid substrate having a high-mobility surface for use with planar and/or multiple-gate metal oxide semiconductor field effect transistors (MOSFETs) is provided. The hybrid substrate has a first surface portion that is optimal for n-type devices, and a second sur... | 02/03/2009 |
| 7485487 | Phase change memory cell with electrode The present invention in one embodiment provides a method of forming a memory device including providing a first dielectric layer including at least one via containing a metal stud; providing a second dielectric layer atop the first dielectric layer; recessing the m... | 02/03/2009 |
| 7485518 | Strained Si MOSFET on tensile-strained SiGe-on-insulator (SGOI) A semiconductor structure for use as a template for forming high-performance metal oxide semiconductor field effect transistor (MOSFET) devices is provided. More specifically, the present invention provides a structure that includes a SiGe-on-insulator substrate inc... | 02/03/2009 |
| 7479437 | Method to reduce contact resistance on thin silicon-on-insulator device A method of reducing contact resistance on a silicon-on-insulator includes exposing sidewalls and a portion of a top surface of a source/drain region of the device, forming a porous silicon layer within a surface of the source/drain region, implanting dopants in the... | 01/20/2009 |
| 7479684 | Field effect transistor including damascene gate with an internal spacer structure A MOSFET is disclosed that comprises a channel between a source extension and a drain extension, a dielectric layer over the channel, a gate spacer structure formed on a peripheral portion of the dielectric layer, and a gate formed on a non-peripheral portion of the... | 01/20/2009 |
| 7473656 | Method for fast and local anneal of anti-ferromagnetic (AF) exchange-biased magnetic stacks A method of thermally treating a magnetic layer of a wafer, includes annealing, for a predetermined short duration, a magnetic layer of a single wafer, applying at least one local magnetic field to the magnetic layer obtained without making electrical contact to the... | 01/06/2009 |
| 7462525 | Enhancement of electron and hole mobilities in <110> Si under biaxial compressive strain The present invention provides a semiconductor material that has enhanced electron and hole mobilities that comprises a Si-containing layer having a crystal orientation and a biaxial compressive strain. The term “biaxial compressive stress” is used herein ... | 12/09/2008 |
| 7456081 | In-place bonding of microstructures A method for bonding microstructures to a semiconductor substrate using attractive forces, such as, hydrophobic, van der Waals, and covalent bonding is provided. The microstructures maintain their absolute position with respect to each other and translate vertically... | 11/25/2008 |
| 7453123 | Self-aligned planar double-gate transistor structure A double-gate transistor having front (upper) and back gates that are aligned laterally is provided. The double-gate transistor includes a back gate thermal oxide layer below a device layer; a back gate electrode below a back gate thermal oxide layer; a front gate t... | 11/18/2008 |
| 7446380 | Stabilization of flatband voltages and threshold voltages in hafnium oxide based silicon transistors for CMOS The present invention provides a metal stack structure that stabilizes the flatband voltage and threshold voltages of material stacks that include a Si-containing conductor and a Hf-based dielectric. This present invention stabilizes the flatband voltages and the th... | 11/04/2008 |
| 7442612 | Nitride-encapsulated FET (NNCFET) A double-gate field effect transistor (DGFET) structure and method of forming such a structure in which the parasitic capacitance under the source/drain regions is substantially reduced are provided. In the present invention, self-aligned isolation regions are provi... | 10/28/2008 |
| 7439542 | Hybrid orientation CMOS with partial insulation process The present invention provides a method of integrated semiconductor devices such that different types of devices are formed upon a specific crystallographic orientation of a hybrid substrate. In accordance with the present invention, junction capacitance of one of t... | 10/21/2008 |
| 7439180 | Dispenser system for atomic beam assisted metal organic chemical vapor deposition (MOCVD) A dispenser system for use in atomic beam assisted metal organic chemical vapor deposition is provided as well as a method of depositing an ultra-thin film using the same. The inventive dispenser system includes an atomic source having an unimpeded line of site to a... | 10/21/2008 |
| 7432550 | Semiconductor structure including mixed rare earth oxide formed on silicon A method (and resultant structure) of forming a semiconductor structure, includes forming a mixed rare earth oxide on silicon. The mixed rare earth oxide is lattice-matched to silicon. ... | 10/07/2008 |
| 7432514 | Method and apparatus for surface potential reflection electron mask lithography A method (and structure) for controlling a beam used to generate a pattern on a target surface includes generating a beam of charged particles and directing the beam to a mask surface and causing the beam to be either absorbed by or reflected from the mask surface, ... | 10/07/2008 |
| 7425483 | Structure and method of fabricating a hybrid substrate for high-performance hybrid-orientation silicon-on-insulator CMOS devices The present invention provides a method of integrating semiconductor devices such that different types of devices are formed upon a specific crystal orientation of a hybrid substrate that enhances the performance of each type of device. Specifically, the present inv... | 09/16/2008 |
| 7423303 | Strained silicon directly-on-insulator substrate with hybrid crystalline orientation and different stress levels The present invention provides a strained Si directly on insulator (SSDOI) substrate having multiple crystallographic orientations and a method of forming thereof. Broadly, but in specific terms, the inventive SSDOI substrate includes a substrate; an insulating laye... | 09/09/2008 |
| 7410625 | Process of making metal containing iron oxide and iron sulfide based nanoparticle materials A method and structure for making magnetite nanoparticle materials by mixing iron salt with alcohol, carboxylic acid and amine in an organic solvent and heating the mixture to 200-360° C. is described. The size of the particles can be controlled either by changing ... | 08/12/2008 |
| 7405436 | Stressed field effect transistors on hybrid orientation substrate A semiconductor structure having improved carrier mobility is provided. The semiconductor structures includes a hybrid oriented semiconductor substrate having at least two planar surfaces of different crystallographic orientation, and at least one CMOS device locate... | 07/29/2008 |
| 7402466 | Strained silicon CMOS on hybrid crystal orientations Methods of forming a strained Si-containing hybrid substrate are provided as well as the strained Si-containing hybrid substrate formed by the methods. In the methods of the present invention, a strained Si layer is formed overlying a regrown semiconductor material,... | 07/22/2008 |
