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| Number | Title | Issue Date |
| 4654599 | Four phase clock signal generator A system for and a method of generating a four phase clock signal is disclosed. The system includes an oscillator circuit that generates a clocking signal of frequency F. A flip-flop, under control of a Master Clear signal, establishes the first stage of ... | 03/31/1987 |
| 4633434 | High performance storage unit A large capacity (8 memory banks of 524K error-corrected 36 bit words stored) high performance (latency as low as 240 nanoseconds, 12.8 gigabits/second aggregate data transfer capability with up to 11.4 gigabits/second utilized) pipelined (8 deep request ... | 12/30/1986 |
| 4628217 | Fast scan/set testable latch using two levels of series gating with one current source An economical circuit of n transistors and m resistors (n=4, m=1 for Emitter Coupled Logic (ECL); n=3, m=0 for Current Mode Logic (CML)) interconnects to a fast differential feedback latch of r transistors and s resistors (r=12, s=9 for ECl; r=7, s=3 for ... | 12/09/1986 |
| 4627018 | Priority requestor accelerator A system for accelerating the granting of prioritized memory requests to a multi port memory system of a data processing system is disclosed. The priority requestor accelerator system detects the fact that one remaining requestor is in the priority memory... | 12/02/1986 |
| 4613860 | Coder-decoder for purged binary block codes Transmitting and receiving apparatus for transmitting data includes a purged code encoder at the transmitter for encoding digital data into constant weight unbalanced codewords representative of the digital data. The constant weight unbalanced codewords c... | 09/23/1986 |
| 4604176 | Method of improving magnetoresistive effect in thin magnetic film A method of fabricating a thin magnetic film having improved magnetoresistive readout characteristics as a binary memory device is disclosed. The film is initially formed from a metal vapor as a series of discrete grains upon a substrate surface that is h... | 08/05/1986 |
| 4600986 | Pipelined split stack with high performance interleaved decode A high performance pipelined virtual first-in first-out stack structure has a data stack portion and a split control stack portion. The stack structure is intended for use in a pipelined high performance storage unit that can pipeline up to R input reques... | 07/15/1986 |
| 4600228 | Lockable compliant end effector apparatus A lockable compliant end effector apparatus is useful with a robotic arm for the automated assembly of electronic equipment. The end effector includes a main body portion having first and second ends. A socket is formed in the first end. A first fluid pas... | 07/15/1986 |
| 4599570 | Phase detector with independent offset correction A method and apparatus of offset correction which can be applied to control systems, primarily phase-locked-loop systems, and which permits sampling of the error signals for use as an auxiliary input to the system in order to center the error signal aroun... | 07/08/1986 |
| 4599036 | Positive registration compliant apparatus for robotic assemblers The problem of re-establishment of initial precision registration of end-effectors used in automatic robotic assembly following failed insertion attempts is avoided due to a positive registration compliant apparatus having a support member including a bea... | 07/08/1986 |
| 4595996 | Programmable video display character control circuit using multi-purpose RAM for display attributes, character generator, and refresh memory A video display control circuit, for an intelligent terminal, includes a large cost efficient Random-Access Memory (RAM). A portion of the RAM memory is utilized as a high speed character generator instead of employing a dedicated Read Only Memory (ROM). ... | 06/17/1986 |
| 4595911 | Programmable data reformat system A high speed system utilizing programmably controlled ranks of multiplexers for reformatting data from programmably selected first formats to second formats is described. Interleaved input data is utilized to optimize reformatting rates. The reformatting ... | 06/17/1986 |
| 4594680 | Apparatus for performing quadratic convergence division in a large data processing system A binary division circuit for use in a large data processing system is disclosed which performs division with floating or fixed point numbers. It includes a multiplier unit which is modified to produce the higher precision calculation necessary to the div... | 06/10/1986 |
| 4592005 | Masked arithmetic logic unit An improved masked arithmetic logic unit is disclosed which incorporates at least three principle unique features to optimize implementation in a high speed environment. These features are (1) the inclusion of a mask operand to facilitate mask compares an... | 05/27/1986 |
| 4590393 | High density gallium arsenide source driven logic circuit A novel high speed gallium arsenide depletion mode field effect transistor logic circuit is provided. One logic input is connected to the source electrode of the switching transistor and draws current when a low level input voltage is provided. Other logi... | 05/20/1986 |
| 4587636 | Y-domain magnetic memory system The memory system incorporates a memory element storing binary digital data in the presence, vel non, of a Y-domain cross-tie. The memory element has a planar contour that is substantially symmetrical about a longitudinal axis and that has edge portions t... | 05/06/1986 |
| 4573254 | Apparatus for maintaining electronic component pin alignment An apparatus for maintaining electronic component pin alignment includes a support member having an adjacent lead shear, a stationary nest, a printed circuit board and a component feeder. A component in the component feeder includes a chip having a plural... | 03/04/1986 |
| 4573155 | Maximum likelihood sequence decoder for linear cyclic codes A novel maximum likelihood sequence detector is provided for decoding linear cyclic error correction codes. The detector comprises one cyclic correlator for each two shaft sets of the code which have weights greater than one, and a serial correlator for d... | 02/25/1986 |
| 4561035 | Method and apparatus for clamping and balancing rotatable members A disc is firmly clamped to the end of a rotatable spindle by a coaxial clamping plate spaced from the spindle end by a ring between the plate and disc surface and attached to the spindle by a single coaxial bolt. The flexible plate, thicker at its center... | 12/24/1985 |
| 4561006 | Integrated circuit package with integral heating circuit An integrated circuit package having an auxiliary heating element incorporated therein is described. The integral heating element is accessible for application of electric power from an external source to cause heating of the integral circuit package to a... | 12/24/1985 |
| 4559459 | High gain non-linear threshold input Josephson junction logic circuit A high gain Josephson junction logic circuit is provided. The novel circuit comprises a high gain non-linear threshold input Josephson junction logic circuit which is coupled to a high gain Josephson junction amplifier. The high gain input circuit provide... | 12/17/1985 |
| 4556978 | Error checked high speed shift matrix A 72-bit shift matrix, suitable for LSI implementation in gate arrays, is disclosed. Eight byte shifters and eight bit shifters are combined to produce shifts of 0-72 places in either direction, circularly or open ended with zero or sign fill. A means is ... | 12/03/1985 |
| 4554664 | Static memory cell with dynamic scan test latch A level sensitive scan design (LSSD) Latch Cell that is adaptable to very large scale integrated (VLSI) Semiconductor circuit fabrication is disclosed. The Latch Cell includes a static functional latch and a dynamic test latch, both of which are controlle... | 11/19/1985 |
| 4551787 | Apparatus for use in cooling integrated circuit chips An integrated circuit chip is cooled by being mounted on a substrate which is urged into contact with a compliant mat which includes a layer having a predetermined array of interconnected metallic pads for spreading heat flux more uniformly. The mat is co... | 11/05/1985 |
| 4549280 | Apparatus for creating a multiplication pipeline of arbitrary size A multiply pipeline with parity circuit to be used as a building block in a multiplication pipeline of arbitrary size is disclosed. It includes circuits for generating and checking parity. The parity of the output carries leaving the component chips of th... | 10/22/1985 |
| 4548111 | Spiral orbital shear apparatus During the assembly of electronic components on circuit boards, the problems of ductile smear cusps produced on wire ends by traditional scissor-type shearing are addressed by a spiral orbital shear apparatus. This apparatus includes a first fixed plate h... | 10/22/1985 |
| 4544963 | Read signal detection in ternary 3PM magnetic recording Circuitry for distinguishing each value in a read signal magnetically recorded in ternary-3 position modulation in which the values 1, 2 and 0 are detected and equalized into a singlet, a doublet and absence of magnetic flux change. The circuitry first de... | 10/01/1985 |
| 4540228 | Low insertion force connector with improved cam actuator A low insertion force connector for making electrical connection between electrical contacts on a printed circuit board assembly and external circuitry, and having an improved linear cam actuating mechanism is described. An elongated outer housing having ... | 09/10/1985 |
| 4536878 | Bit serial convolutional decoder for VLSI implementation A decoder for forward-error-correcting (FEC) convolutional codes. The decoder uses the Viterbi algorithm for decoding the rate 1/2, constraint length 7 code with generator polynomials x6 +x5 +x3 +x2 +1, and x | 08/20/1985 |
| 4535420 | Circular-queue structure Apparatus for producing a circular-queue structure which permits interfacing between a high speed mini-computer and a relatively slow speed microprocessor via a common memory and with multi-device, asynchronous handling capability. The structure also perm... | 08/13/1985 |
| 4534608 | Shielded connector shell for flat cable A shell for a connector for flat shielded cable. The shell is formed of conductive material and is constructed so as physically and electrically to contact the shield so that grounding the shell will ground the shield. The shell also includes portions to ... | 08/13/1985 |
| 4533624 | Method of forming a low temperature multilayer photoresist lift-off pattern A novel multilayer lift-off pattern of positive and negative photoresist materials is provided. A positive first layer is deposited on a substrate and flood exposed before a subsequent layer of negative photoresist material is added on top of the positive... | 08/06/1985 |
| 4531213 | Memory through checking system with comparison of data word parity before and after ECC processing For use with a digital memory system that generates error correction code signals for storage with associated data words and for correction of detected error(s) in the associated data words when accessed, a system for through checking the accuracy of gene... | 07/23/1985 |
| 4529324 | Spindle bearing follower This invention is a device to reduce the wobble of a rotating shaft disposed in a cavity of a housing which wobble results from a spurious or undesirable positioning of a bearing assembly in which the shaft rotates. The present device includes a bearing f... | 07/16/1985 |
| 4528665 | Gray code counter with error detector in a memory system An improved dynamic memory system including through-checking and error detection of the refresh counter is described. A refresh counter that provides parity of the refresh count for through-checking, of refresh addresses is shown. Error detecting circuitr... | 07/09/1985 |
| 4528648 | Memory management system A unique memory management system for use with a memory device which is common (or shared) with a plurality of user elements utilizing a memory address counter, scratch pad address memory, external memory address inputs and an address multiplexer.... | 07/09/1985 |
| 4528640 | Method and a means for checking normalizing operations in a computer device A method and a means are disclosed for the throughchecking of the normalizer operations of an arithmetic unit of a data processing system involving both integer and floating-point formats in single and double precision operations. A post normalizer is use... | 07/09/1985 |
| 4527075 | Clock source with automatic duty cycle correction A clock source for timing and synchronizing the operation of digital data processing equipment and having automatic duty cycle correction is described. A source of signals provides clock signals at a predetermined frequency. A buffer circuit provides the ... | 07/02/1985 |
| 4523314 | Read error occurrence detector for error checking and correcting system An improved error indicating system utilizing adder circuits for use with an error correction code system capable of detecting and indicating multiple bit errors and detecting and correcting single bit errors is described. The system utilizes an encoding ... | 06/11/1985 |
| 4523210 | Fast error checked multibit multiplier A high speed multiplier circuit is disclosed which not only provides increased performance for the multiply operations of a large scale processor but also provides for single bit error detection of results as well. It incorporates a gated carry/save adder... | 06/11/1985 |
