Bizarre Patents
Method and apparatus for making a drink hop along a bar or counter
A method for generating a drink which appears to hop from a remote spot on the bar or counter and take one or more leaps, before landing in a patron's glass.
PatentStorm News
Make the Most of Our Site
See this month's Top Inventors and Most Cited Patents.
Stay on top of the latest innovations by subscribing to an RSS feed.
Registered users: Manage your profile.
| Number | Title | Issue Date |
| 7808039 | SOI transistor with merged lateral bipolar transistor A semiconductor-on-insulator transistor device includes a source region, a drain region, a body region, and a source-side lateral bipolar transistor. The source region has a first conductivity type. The body region has a second conductivity type and is positioned be... | 10/05/2010 |
| 7565293 | Seamless hybrid computer human call service A Voice User Interface is provided for interactively responding in a synthesized voice to a call from a human caller, a Text to Speech system by which text entered by an agent and interactive data are converted to synthesized speech, a morphing transformation librar... | 07/21/2009 |
| 7544610 | Method and process for forming a self-aligned silicide contact The present invention provides a method for forming a self-aligned Ni alloy silicide contact. The method of the present invention begins by first depositing a conductive Ni alloy with Pt and optionally at least one of the following metals Pd, Rh, Ti, V, Cr, Zr, Nb, ... | 06/09/2009 |
| 7537709 | Method for isotropic etching of copper Copper and copper alloys are etched to provide uniform and smooth surface by employing an aqueous composition that comprises an oxidant, a mixture of at least one weak complexant and at least one strong complexant for the copper or copper alloy, and water and has a ... | 05/26/2009 |
| 7534696 | Multilayer interconnect structure containing air gaps and method for making A multilevel air-gap-containing interconnect structure and a method of fabricating the same are provided. The multilevel air-gap-containing interconnect structure includes a collection of interspersed line levels and via levels, with via levels comprising conductive... | 05/19/2009 |
| 7528065 | Structure and method for MOSFET gate electrode landing pad A transistor device and method of forming the same comprises a substrate; a first gate electrode over the substrate; a second gate electrode over the substrate; and a landing pad comprising a pair of flanged ends overlapping the second gate electrode, wherein the st... | 05/05/2009 |
| 7525162 | Orientation-optimized PFETS in CMOS devices employing dual stress liners A PFET is provided on a silicon layer having a (110) surface orientation and located in a substrate. A compressive stress liner disposed on the gate and source/drain regions of the PFET generates a primary longitudinal compressive strain along the direction of the P... | 04/28/2009 |
| 7521377 | SiCOH film preparation using precursors with built-in porogen functionality A method of fabricating a dielectric material that has an ultra low dielectric constant (or ultra low k) using at least one organosilicon precursor is described. The organosilicon precursor employed in the present invention includes a molecule containing both an Siâ... | 04/21/2009 |
| 7521376 | Method of forming a semiconductor structure using a non-oxygen chalcogen passivation treatment A method and structure in which Ge-based semiconductor devices such as FETs and MOS capacitors can be obtained are provided. Specifically, the present invention provides a method of forming a semiconductor device including a stack including a dielectric layer and a ... | 04/21/2009 |
| 7517795 | Stabilization of Ni monosilicide thin films in CMOS devices using implantation of ions before silicidation A method for forming a stabilized metal silicide film, e.g., contact (source/drain or gate), that does not substantially agglomerate during subsequent thermal treatments, is provided In the present invention, ions that are capable of attaching to defects within the ... | 04/14/2009 |
| 7510904 | Structure for and method of fabricating a high-speed CMOS-compatible Ge-on-insulator photodetector The invention addresses the problem of creating a high-speed, high-efficiency photodetector that is compatible with Si CMOS technology. The structure consists of a Ge absorbing layer on a thin SOI substrate, and utilizes isolation regions, alternating n- and p-type ... | 03/31/2009 |
| 7507988 | Semiconductor heterostructure including a substantially relaxed, low defect density SiGe layer A heterostructure is provided which includes a substantially relaxed SiGe layer present atop an insulating region that is located on a substrate. The substantially relaxed SiGe layer has a thickness of from about 2000 nm or less, a measured lattice relaxation of fro... | 03/24/2009 |
| 7504727 | Semiconductor interconnect structure utilizing a porous dielectric material as an etch stop layer between adjacent non-porous dielectric materials Interconnect structures possessing a non-porous (dense) low-k organosilicate glass (OSG) film utilizing a porous low-k OSG film as an etch stop layer or a porous low-k OSG film using a non-porous OSG film as a hardmask for use in semiconductor devices are provided h... | 03/17/2009 |
| 7501318 | Formation of silicon-germanium-on-insulator (SGOI) by an integral high temperature SIMOX-Ge interdiffusion anneal A method of forming a substantially relaxed, high-quality SiGe-on-insulator substrate material using SIMOX and Ge interdiffusion is provided. The method includes first implanting ions into a Si-containing substrate to form an implant rich region in the Si-containing... | 03/10/2009 |
| 7498254 | Plating seed layer including an oxygen/nitrogen transition region for barrier enhancement An interconnect structure which includes a plating seed layer that has enhanced conductive material, preferably, Cu, diffusion properties is provided that eliminates the need for utilizing separate diffusion and seed layers. Specifically, the present invention provi... | 03/03/2009 |
| 7498235 | Method for fabricating SiGe-on-insulator (SGOI) and Ge-on-insulator (GOI) substrates A method for fabricating germanium-on-insulator (GOI) substrate materials, the GOI substrate materials produced by the method and various structures that can include at least the GOI substrate materials of the present invention are provided. The GOI substrate materi... | 03/03/2009 |
| 7494886 | Uniaxial strain relaxation of biaxial-strained thin films using ion implantation A method for achieving uniaxial strain on originally biaxial-strained thin films after uniaxial strain relaxation induced by ion implantation is provided. The biaxial-strained thin film receives ion implantation after being covered by a patterned implant block struc... | 02/24/2009 |
| 7492008 | Control of buried oxide in SIMOX A method for forming a semiconductor-on-insulator (SOI) substrate is described incorporating the steps of heating a substrate, implanting oxygen into a heated substrate, cooling the substrate, implanting into a cooled substrate and annealing. The steps of implanting... | 02/17/2009 |
| 7491643 | Method and structure for reducing contact resistance between silicide contact and overlying metallization A semiconductor structure in which the contact resistance in the contact opening is reduced as well as a method of forming the same are provided. This is achieved in the present invention by replacing conventional contact metallurgy, such as tungsten, or a metal sil... | 02/17/2009 |
| 7491658 | Ultra low k plasma enhanced chemical vapor deposition processes using a single bifunctional precursor containing both a SiCOH matrix functionality and organic porogen functionality A method for fabricating a SiCOH dielectric material comprising Si, C, O and H atoms from a single organosilicon precursor with a built-in organic porogen is provided. The single organosilicon precursor with a built-in organic porogen is selected from silane (SiH | 02/17/2009 |
| 7488677 | Interconnect structures with encasing cap and methods of making thereof A method of making an interconnect that includes providing an interconnect structure in a dielectric material, recessing the dielectric material such that a portion of the interconnect structure extends above an upper surface of the dielectric; and depositing an enc... | 02/10/2009 |
| 7485539 | Strained semiconductor-on-insulator (sSOI) by a simox method A strained (tensile or compressive) semiconductor-on-insulator material is provided in which a single semiconductor wafer and a separation by ion implantation of oxygen process are used. The separation by ion implantation of oxygen process, which includes oxygen ion... | 02/03/2009 |
| 7485582 | Hardmask for improved reliability of silicon based dielectrics The present invention provides a hardmask that is located on a surface of a low k dielectric material having at least one conductive feature embedded therein. The hardmask includes a lower region of a hermetic oxide material located adjacent to the low k dielectric ... | 02/03/2009 |
| 7482243 | Ultra-thin Si channel MOSFET using a self-aligned oxygen implant and damascene technique The present invention provides a method of forming a thin channel MOSFET having low external resistance. The method comprises forming a dummy gate region atop a substrate; implanting oxide forming dopant through said dummy gate to create a localized oxide region in ... | 01/27/2009 |
| 7479418 | Methods of applying substrate bias to SOI CMOS circuits The present invention relates to methods for reducing the threshold voltage difference between an n-type field effect transistor (n-FET) and a p-type field effect transistor (p-FET) in a complementary metal-oxide-semiconductor (CMOS) circuit located on a silicon-on-... | 01/20/2009 |
| 7479306 | SiCOH dielectric material with improved toughness and improved Si-C bonding, semiconductor device containing the same, and method to make the same A low-k dielectric material with increased cohesive strength for use in electronic structures including interconnect and sensing structures is provided that includes atoms of Si, C, O, and H in which a fraction of the C atoms are bonded as Si—CH3 functi... | 01/20/2009 |
| 7479683 | Selective implementation of barrier layers to achieve threshold voltage control in CMOS device fabrication with high-k dielectrics The present invention provides a semiconductor structure including a semiconductor substrate having a plurality of source and drain diffusion regions located therein, each pair of source and drain diffusion regions are separated by a device channel. The structure fu... | 01/20/2009 |
| 7473975 | Fully silicided metal gate semiconductor device structure A method for forming a semiconductor device structure, comprising the steps of independently forming source/drain surface metal silicide layers and a fully silicided metal gate in a polysilicon gate stack. Specifically, one or more sets of spacer structures are prov... | 01/06/2009 |
| 7473587 | High-quality SGOI by oxidation near the alloy melting temperature A method of forming a low-defect, substantially relaxed SiGe-on-insulator substrate material is provided. The method includes first forming a Ge-containing layer on a surface of a first single crystal Si layer which is present atop a barrier layer that is resistant ... | 01/06/2009 |
| 7465992 | Field effect transistor with mixed-crystal-orientation channel and source/drain regions Hybrid orientation substrates allow the fabrication of complementary metal oxide semiconductor (CMOS) circuits in which the n-type field effect transistors (nFETs) are disposed in a semiconductor orientation which is optimal for electron mobility and the p-type fiel... | 12/16/2008 |
| 7456046 | Method to create flexible connections for integrated circuits A method of producing flexible interconnections for integrated circuits, and, in particular, the forming of flexible or compliant interconnections preferably by a laser-assisted chemical vapor deposition process in semiconductor or glass substrate-based carriers whi... | 11/25/2008 |
| 7456045 | Low temperature melt-processing of organic-inorganic hybrid The present invention provides a process for preparing a melt-processed organic-inorganic hybrid material including the steps of maintaining a solid organic-inorganic hybrid material at a temperature above the melting point but below the decomposition temperature of... | 11/25/2008 |
| 7452767 | Selective implementation of barrier layers to achieve threshold voltage control in CMOS device fabrication with high k dielectrics A method of forming a CMOS structure, and the device produced therefrom, having improved threshold voltage and flatband voltage stability. The inventive method includes the steps of providing a semiconductor substrate having an nFET region and a pFET region; forming... | 11/18/2008 |
| 7449782 | Self-aligned metal to form contacts to Ge containing substrates and structure formed thereby A method for forming germano-silicide contacts atop a Ge-containing layer that is more resistant to etching than are conventional silicide contacts that are formed from a pure metal is provided. The method of the present invention includes first providing a structur... | 11/11/2008 |
| 7445977 | Method of creating defect free high Ge content (> 25%) SiGe-on-insulator (SGOI) substrates using wafer bonding techniques A method for achieving a substantially defect free SGOI substrate which includes a SiGe layer that has a high Ge content of greater than about 25 atomic % using a low temperature wafer bonding technique is described. The wafer bonding process described in the presen... | 11/04/2008 |
| 7446058 | Adhesion enhancement for metal/dielectric interface An interconnect structure and method of fabricating the same in which the adhesion between a chemically etched dielectric material and a noble metal liner is improved are provided. In accordance with the present invention, a chemically etching dielectric material is... | 11/04/2008 |
| 7446025 | Method of forming vertical FET with nanowire channels and a silicided bottom contact A vertical FET structure with nanowire forming the FET channels is disclosed. The nanowires are formed over a conductive silicide layer. The nanowires are gated by a surrounding gate. Top and bottom insulator plugs function as gate spacers and reduce the gate-source... | 11/04/2008 |
| 7446942 | Injection molded microlenses for optical interconnects Disclosed are a microlens array, and a method of positioning and aligning the microlens array on another device. Generally, the microlens array comprises an array of injection molded microlens elements, and a supporting flange. Each of the microlens elements has a g... | 11/04/2008 |
| 7442993 | Ultra-thin, high quality strained silicon-on-insulator formed by elastic strain transfer A method of forming a semiconductor structure comprising a first strained semiconductor layer over an insulating layer is provided in which the first strained semiconductor layer is relatively thin (less than about 500 â„«) and has a low defect density (stacking fau... | 10/28/2008 |
| 7444544 | Write filter cache method and apparatus for protecting the microprocessor core from soft errors A write filter cache system for protecting a microprocessor core from soft errors and method thereof are provided. In one aspect, data coming from a processor core to be written in primary cache memory, for instance, L1 cache memory system, is buffered in a write fi... | 10/28/2008 |
