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Cloaking System Using Optoelectronically Controlled Camouflage
A Cloaking System designed to operate in the visible light spectrum, utilizes optoelectronics and/or photonic components to conceal an object within it.
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| Number | Title | Issue Date |
| 8138410 | Optical tandem photovoltaic cell panels A solar energy conversion device comprises a vertical stack of at least two panels stacked in a hierarchy from an upper panel to a lower panel with each of the panels including a matching array of solar cells having a different energy bandgap from other panels of so... | 03/20/2012 |
| 8101856 | Quantum well GaP/Si tandem photovoltaic cells Two junction solar energy conversion devices, i.e. photovoltaic cells have a bottom silicon N+/P/P+ photovoltaic cell and an upper GaP N+/P/P+ photovoltaic cell containing quantum well layers which extend the wavelength range over which the GaP cell absorbs light. T... | 01/24/2012 |
| 8076756 | Structure for inhibiting back end of line damage from dicing and chip packaging interaction failures A semiconductor product comprises a semiconductor substrate having a top surface and a bottom surface including a semiconductor chip. The semiconductor substrate has a top surface and a perimeter. A barrier is formed in the chip within the perimeter. An Ultra Deep I... | 12/13/2011 |
| 7955955 | Using crack arrestor for inhibiting damage from dicing and chip packaging interaction failures in back end of line structures A semiconductor product comprises a semiconductor substrate having a top surface and a bottom surface including a semiconductor chip. The semiconductor substrate has a top surface and a perimeter. A barrier is formed in the chip within the perimeter. An Ultra Deep I... | 06/07/2011 |
| 7923712 | Phase change memory element with a peripheral connection to a thin film electrode A PCM cell structure comprises a first electrode, a phase change element, and a second electrode, wherein the phase change element is inserted in between the first electrode and the second electrode and only the peripheral edge of the first electrode contacts the ph... | 04/12/2011 |
| 7892956 | Methods of manufacture of vertical nanowire FET devices A vertical Field Effect Transistor (FET) comprising a vertical semiconductor nanowire is formed by the following steps. Create a columnar pore in a bottom dielectric layer formed on a bottom electrode. Fill the columnar pore by plating a vertical semiconductor nanow... | 02/22/2011 |
| 7855101 | Layer transfer process and functionally enhanced integrated circuits produced thereby A structure for a semiconductor components is provided having a device layer sandwiched on both sides by other active, passive, and interconnecting components. A wafer-level layer transfer process is used to create this planar (2D) IC structure with added functional... | 12/21/2010 |
| 7825000 | Method for integration of magnetic random access memories with improved lithographic alignment to magnetic tunnel junctions A magnetic memory device including a Magnetic Tunnel Junction (MTJ) device comprises a substrate and Front End of Line (FEOL) circuitry. A Via level (VA) InterLayer Dielectric (ILD) layer, a bottom conductor layer, and an MTJ device formed over the top surface of th... | 11/02/2010 |
| 7773220 | Method and system for collecting alignment data from coated chips or wafers A process and system for determining alignment data for partially obscured features on wafers or chips when a wafer or chip is substantially coated by an over bump applied material, e.g. a resin or film, and using that data to align the wafers or chips for subsequen... | 08/10/2010 |
| 7700993 | CMOS EPROM and EEPROM devices and programmable CMOS inverters A CMOS EPROM, EEPROM or inverter device includes an nFET device with a thin gate dielectric layer and a pFET device juxtaposed with the nFET device with a thick gate dielectric layer and a floating gate electrode. The thick gate dielectric layer is substantially thi... | 04/20/2010 |
| 7642549 | Phase change memory cells delineated by regions of modified film resistivity A Phase Change Memory (PCM) cell structure comprises both a lower electrode composed of a PCM layer and a conductive encapsulating upper electrode layer. The PCM layer is protected from damage by the conductive encapsulating layer. Electrical isolation between adjac... | 01/05/2010 |
| 7601627 | Method for reduction of soft error rates in integrated circuits A method for reduction of soft error rates in integrated circuits. The method including: providing a test device, the test device comprising: a semiconductor substrate; and a stack of one or more wiring levels stacked from a lowermost wiring level to an uppermost wi... | 10/13/2009 |
| 7598616 | Interconnect structure A structure. The structure includes: a core electrical conductor having a top surface, an opposite bottom surface and sides between the top and bottom surfaces; an electrically conductive liner in direct physical contact with and covering the bottom surface and the ... | 10/06/2009 |
| 7563710 | Method of fabrication of interconnect structures A method of forming a damascene wire. The method including: forming a mask layer on a top surface of a dielectric layer; forming an opening in the mask layer; forming a trench in the dielectric layer where the dielectric layer is not protected by the mask layer; rec... | 07/21/2009 |
| 7563657 | High performance FET devices and methods thereof Structure and methods of fabrication are disclosed for an enhanced FET devices in which dopant impurities are prevented from diffusing through the gate insulator. The structure comprises a Si:C, or SiGe:C, layer which is sandwiched between the gate insulator and a l... | 07/21/2009 |
| 7550361 | Trench structure and method for co-alignment of mixed optical and electron beam lithographic fabrication levels A method for aligning a first set of features of a fabrication level of an integrated circuit chip to an electron beam alignment target formed in a substrate and forming the first set of features using electron beam lithography and for aligning a second set of featu... | 06/23/2009 |
| 7550313 | Method for delineation of phase change memory (PCM) cells separated by PCM and upper electrode regions modified to have high film resistivity A method for forming a Phase Change Material (PCM) cell structure comprises forming both a lower electrode composed of a PCM layer and a conductive encapsulating upper electrode layer. The PCM is protected from damage by a conductive encapsulating layer. Electrical ... | 06/23/2009 |
| 7547930 | High performance FET devices and methods thereof Structure and methods of fabrication are disclosed for an enhanced FET devices in which dopant impurities are prevented from diffusing through the gate insulator. The structure comprises a Si:C, or SiGe:C, layer which is sandwiched between the gate insulator and a l... | 06/16/2009 |
| 7542330 | SRAM with asymmetrical pass gates An SRAM having asymmetrical FET pass gates and a method of fabricating an SRAM having asymmetrical FET pass gates. The pass gates are asymmetrical with respect to current conduction from the drain to the source of the pass gate being different from current conductio... | 06/02/2009 |
| 7539979 | Method and system for forcing context-switch during mid-access to non-atomic variables The invention provides an improved method for detecting concurrent bugs in multi-threaded software having at least one command to access a non-atomic variable. The non-atomic variable may have a plurality of memory words. In one approach, the method generally involv... | 05/26/2009 |
| 7531407 | Semiconductor integrated circuit devices having high-Q wafer backside inductors and methods of fabricating same Methods are provided for fabricating semiconductor IC (integrated circuit) chips having high-Q on-chip inductors formed on the chip backside and connected to integrated circuits on the chip frontside using through-wafer interconnects. For example, a semiconductor de... | 05/12/2009 |
| 7530056 | Method and system for detecting runtime defects in a program by comparing correct and incorrect runs The invention provides an improved method and method for locating the origin of runtime defect in software programs. A differential debugging technique may be implemented to locate the diversion point where two programs start to behave differently. In one approach, ... | 05/05/2009 |
| 7528493 | Interconnect structure and method of fabrication of same A damascene wire and method of forming the wire. The method including: forming a mask layer on a top surface of a dielectric layer; forming an opening in the mask layer; forming a trench in the dielectric layer where the dielectric layer is not protected by the mask... | 05/05/2009 |
| 7510916 | High performance FET devices and methods thereof Structure and methods of fabrication are disclosed for an enhanced FET devices in which dopant impurities are prevented from diffusing through the gate insulator. The structure comprises a Si:C, or SiGe:C, layer which is sandwiched between the gate insulator and a l... | 03/31/2009 |
| 7495338 | Metal capped copper interconnect A conducting material comprising: a conducting core region comprising copper and from 0.001 atomic percent to 0.6 atomic percent of one or more metals selected from iridium, osmium and rhenium; and an interfacial region. The interfacial region comprises at least 80 ... | 02/24/2009 |
| 7494861 | Method for metal gated ultra short MOSFET devices MOSFET devices suitable for operation at gate lengths less than about 40 nm, and methods of their fabrication is being presented. The MOSFET devices include a ground plane formed of a monocrystalline Si based material. A Si based body layer is epitaxially disposed o... | 02/24/2009 |
| 7491948 | Method of detecting and transmitting radiation detection information to a network A method of detecting and transmitting radiation detection information to a network. The method including: communicating with one or more personal radiation detection devices, each device including, a host memory, an event memory, a microprocessor, a global position... | 02/17/2009 |
| 7492821 | System and method for selective image capture, transmission and reconstruction A video processing method and system for generating a foveated video display with sections having different resolutions uses a network channel for communicating video images having video sections of different resolutions, and includes a video transmission system for... | 02/17/2009 |
| 7486369 | Liquid crystal display and method for manufacturing liquid crystal display A liquid crystal display having an injection hole post structures compatible with liquid crystal are formed in an area near an injection hole to prevent pollutants seeped from an end-sealing material from penetrating into a display area, thereby suppressing the occu... | 02/03/2009 |
| 7486525 | Temporary chip attach carrier A temporary chip attach carrier for and a method of testing an integrated circuit chip. The carrier includes: a substrate, a first array of interconnects disposed on a bottom surface and a second array of interconnects disposed on a top surface of the substrate, cor... | 02/03/2009 |
| 7484075 | Method and apparatus for providing fast remote register access in a clustered VLIW processor using partitioned register files Effective remote register file access time can be reduced in a clustered VLIW processor using partitioned register files and some additional hardware for pre-fetching remote registers. An instruction pre-fetcher and an instruction pre-decoder is used for pre-fetchin... | 01/27/2009 |
| 7478417 | Broadcast system and method for browsing the web The present invention provides a method and apparatus to browse the Web without using a web browser. The application server in a transmitting unit converts a web page transmitted from the Internet into video data and provides links to the video data on the basis of ... | 01/13/2009 |
| 7473979 | Semiconductor integrated circuit devices having high-Q wafer back-side capacitors Methods are provided for fabricating semiconductor IC (integrated circuit) chips having high-Q on-chip capacitors formed on the chip back-side and connected to integrated circuits on the chip front-side using through-wafer interconnects. In one aspect, a semiconduct... | 01/06/2009 |
| 7471826 | Character segmentation by slices A method for segmentation of characters in text that segments text into lines, words and slices and determines at least one of fixed pitch and proportional pitch prior to segmentation. The method computes histograms of the lines and defines widths of lobes of the hi... | 12/30/2008 |
| 7468320 | Reduced electromigration and stressed induced migration of copper wires by surface coating The idea of the invention is to coat the free surface of patterned Cu conducting lines in on-chip interconnections (BEOL) wiring by a 1-20 nm thick metal layer prior to deposition of the interlevel dielectric. This coating is sufficiently thin so as to obviate the n... | 12/23/2008 |
| 7467288 | Vector register file with arbitrary vector addressing A system and method for processing operations that use data vectors each comprising a plurality of data elements, in accordance with the present invention, includes a vector data file comprising a plurality of storage elements for storing data elements of the data v... | 12/16/2008 |
| 7449067 | Method and apparatus for filling vias A method for filling vias, and in particular initially blind vias, in a wafer, and various apparatus for performing the method, comprising evacuating air from the vias; trapping at least a portion of the wafer and a paste for filling the vias between two surfaces; a... | 11/11/2008 |
| 7446040 | Structure for optimizing fill in semiconductor features deposited by electroplating A structure and process are provided that are capable of reducing the occurrence of discontinuities within the metallization, such as voiding or seams, formed during electroplating at the edges of semiconductor metallization arrays. The structure includes a metalliz... | 11/04/2008 |
| 7434308 | Cooling of substrate using interposer channels A structure, and method of forming and cooling the structure. The structure may include a substrate (e.g., a semiconductor chip) having N continuous substrate channels and an interposer having N continuous interposer channels (N≧2). The N interposer channels are c... | 10/14/2008 |
| 7413941 | Method of fabricating sectional field effect devices A field effect device is disclosed which has a body formed of a crystalline semiconductor material and has at least one vertically oriented section and at least one horizontally oriented section. The device is produced in SOI technology by fabricating first a format... | 08/19/2008 |
