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| Number | Title | Issue Date |
| 8181131 | Enhanced analysis of array-based netlists via reparameterization A mechanism is provided for increasing the scalability of formal verification solutions through enabling the use of input reparameterization on logic models that include memory arrays. A pre-processing mechanism enables the selection of a cut-based design partition ... | 05/15/2012 |
| 8176355 | Recovery from hardware access errors A mechanism is provided for recovering from a data scan error. A service processor determines the nature of the data scan error and, depending on the nature of the error, performs one of a plurality of data scan error recovery procedures. ... | 05/08/2012 |
| 8171476 | Wake-and-go mechanism with prioritization of threads A hardware private array is a thread state storage that is embedded within the processor or within logic associated with a bus or wake-and-go logic. The hardware private array and/or wake-and-go array may have a limited storage area. Therefore, each thread may have ... | 05/01/2012 |
| 8166408 | Management of virtual discussion threads in a synchronous conferencing system A mechanism is provided for defining and managing virtual discussion threads in a generic synchronous conferencing system. A chat server and chat client define a virtual discussion thread (VDT) entity that includes a group of chat entries or parts of chat entries. T... | 04/24/2012 |
| 8161493 | Weighted-region cycle accounting for multi-threaded processor cores An aspect of the present invention improves the accuracy of measuring processor utilization of multi-threaded cores by providing a calibration facility that derives utilization in the context of the overall dynamic operating state of the core by assigning weights to... | 04/17/2012 |
| 8158461 | Continuously referencing signals over multiple layers in laminate packages A mechanism for continuously referencing signals over multiple layers in laminate packages provides a continuous path for signals from one layer to another while using the ideal voltage reference for all areas of the package and still avoiding discontinuities in the... | 04/17/2012 |
| 8156498 | Optimization of thread wake up for shared processor partitions A mechanism is provided for biasing placement of a software thread on a currently idle and dispatched processor. The operating system starts with the last logical processor on which the software thread ran and determines whether that processor is idle and dispatched... | 04/10/2012 |
| 8156497 | Providing shared tasks amongst a plurality of individuals A mechanism for sharing tasks is provided in which individuals in a share group may signal their intent to complete individual shared tasks and communicate that intent to other individuals in the share group. A required time for completion of the shared tasks may be... | 04/10/2012 |
| 8156226 | Ordering provisioning request execution based on service level agreement and customer entitlement A solution provided here comprises receiving requests for a service from a plurality of customers, responding to the requests for a service, utilizing a shared infrastructure, and configuring the shared infrastructure, based on stored customer information. Another e... | 04/10/2012 |
| 8146034 | Efficient Redundancy Identification, Redundancy Removal, and Sequential Equivalence Checking within Designs Including Memory Arrays. A mechanism is provided for efficient redundancy identification, redundancy removal, and sequential equivalence checking with designs including memory arrays. The mechanism includes an array merging component to optimally merge an array output such that if the addre... | 03/27/2012 |
| 8145849 | Wake-and-go mechanism with system bus response A wake-and-go mechanism is provided for a data processing system. The wake-and-go mechanism is configured to issue a look-ahead load command on a system bus to read a data value from a target address and perform a comparison operation to determine whether the data v... | 03/27/2012 |
| 8145723 | Complex remote update programming idiom accelerator A remote update programming idiom accelerator is configured to detect a complex remote update programming idiom in an instruction sequence of a thread. The complex remote update programming idiom includes a read operation for reading data from a storage location at ... | 03/27/2012 |
| 8141078 | Providing shared tasks amongst a plurality of individuals A mechanism for sharing tasks is provided in which individuals in a share group may signal their intent to complete individual shared tasks and communicate that intent to other individuals in the share group. A required time for completion of the shared tasks may be... | 03/20/2012 |
| 8141067 | Ensuring maximum code motion of accesses to DMA buffers A “kill” intrinsic that may be used in programs for designating specific data objects as having been “killed” by a preceding action is provided. The concept of a data object being “killed” is that the compiler is informed that no operations (e.g., loads ... | 03/20/2012 |
| 8140902 | Internally controlling and enhancing advanced test and characterization in a multiple core microprocessor A mechanism is provided for internally controlling and enhancing advanced test and characterization in a multiple core microprocessor. To decrease the time needed to test a multiple core chip, the mechanism uses micro-architectural support that allows one core, a co... | 03/20/2012 |
| 8140824 | Secure code authentication A computer program product comprises a computer useable medium having a computer readable program for authentication of code, such as boot code. A memory addressing engine is employable to select a portion of a memory, as a function of a step value, as a first input... | 03/20/2012 |
| 8140573 | Exporting and importing business objects based on metadata A metadata file can be automatically generated based on a database instance and a user defined maximum depth. The relationships between data objects that constitute a business object may be visualized in a tree. The maximum depth limits the number of levels in the t... | 03/20/2012 |
| 8131673 | Background file sharing in a segmented peer-to-peer file sharing network A peer-to-peer file sharing client with background file sharing is provided in a segmented peer-to-peer file sharing network. Each file sharing participant may designate an amount of bandwidth and/or storage space for background file sharing. Peer-to-peer file shari... | 03/06/2012 |
| 8128498 | Configure offline player behavior within a persistent world game A mechanism is provided for configuring offline player behavior within a persistent world game. A player agent for an offline player includes an event monitor that monitors for events that occur in a persistent virtual world maintained by a game server. When a game ... | 03/06/2012 |
| 8127080 | Wake-and-go mechanism with system address bus transaction master A wake-and-go mechanism is provided for a data processing system. The wake-and-go mechanism is configured to issue a look-ahead load command on a system bus to read a data value from a target address and perform a comparison operation to determine whether the data v... | 02/28/2012 |
| 8122342 | Enforcing accessible content development A mechanism is provided for enforcing accessible content development. The mechanism enforces accessible content development by accessing a tag library descriptor for each of a plurality of markup tags for web content authoring where the tag library descriptor notes ... | 02/21/2012 |
| 8122312 | Internally controlling and enhancing logic built-in self test in a multiple core microprocessor A mechanism is provided for internally controlling and enhancing logic built-in self test in a multiple core microprocessor. The control core may use architectural support for scan and external scan communication (XSCOM) to independently test the other cores while a... | 02/21/2012 |
| 8108866 | Heuristic based affinity dispatching for shared processor partition dispatching A mechanism is provided for determining whether to use cache affinity as a criterion for software thread dispatching in a shared processor logical partitioning data processing system. The server firmware may store data about when and/or how often logical processors ... | 01/31/2012 |
| 8108415 | Query transformation A mechanism is provided for transforming an original database query into a supported database query that can be fully computed by a target database. The original database query comprising a select list including a plurality of expressions, the plurality of expressio... | 01/31/2012 |
| 8099634 | Autonomic component service state management for a multiple function component A mechanism is provided for autonomic component service state management for a multiple function component. The mechanism determines whether independent functions within a multiple function service boundary can be serviced. When a single function experiences a failu... | 01/17/2012 |
| 8099532 | Intelligent dynamic multi-zone single expander connecting dual ported drives A single fibre channel switch or serial attached SCSI expander applies zoning on the initiator ports to each of the two ports of one or more drives. The fibre channel switch or serial attached SCSI expander uses zoning to connect both ports of each drive to a single... | 01/17/2012 |
| 8093868 | In situ verification of capacitive power support A mechanism for in situ verification of capacitive power support is provided. A memory system uses a super capacitor to support a voltage rail when input power is lost or interrupted. The voltage discharge curve is a function of load and capacitance of the component... | 01/10/2012 |
| 8086826 | Dependency tracking for enabling successive processor instructions to issue An information handling system includes a processor with an issue unit (IU) that may perform instruction dependency tracking for successive instruction issue operations. The IU maintains non-shifting issue queue (NSIQ) and shifting issue queue (SIQ) instructions alo... | 12/27/2011 |
| 8086801 | Loading data to vector renamed register from across multiple cache lines A load instruction that accesses data cache may be off natural alignment, which causes a cache line crossing to complete the access. The illustrative embodiments provide a mechanism for loading data across multiple cache lines without the need for an accumulation re... | 12/27/2011 |
| 8082315 | Programming idiom accelerator for remote update A remote update programming idiom accelerator identifies a remote update programming idiom in an instruction sequence of a thread running on a processing unit of a data processing system. The remote update programming idiom includes a read operation for reading data... | 12/20/2011 |
| 8065372 | Publish/subscribe messaging The invention relates to a message brokering system for connecting a client in a local publish/subscribe messaging system to a remote message broker. The system comprises a message broker in said local publish/subscribe messaging system and a metabroker application ... | 11/22/2011 |
| 8051228 | Physical interface macros (PHYS) supporting heterogeneous electrical properties An integrated processor design includes physical interface macros supporting heterogeneous electrical properties. The processor design comprises a plurality of processing cores and a plurality of physical interfaces to connect to a memory interface, a peripheral com... | 11/01/2011 |
| 8046574 | Secure boot across a plurality of processors Boot code is partitioned into a plurality of boot code partitions. Processors of a multiprocessor system are selected to be boot processors and are each provided with a boot code partition to execute in a predetermined boot code sequence. Each processor executes its... | 10/25/2011 |
| 8046573 | Masking a hardware boot sequence One of the processors of a multiprocessor system is chosen to be a boot processor. The other processors of the multiprocessor system execute masking code that generates electromagnetic and/or thermal signatures that mask the electromagnetic and/or thermal signatures... | 10/25/2011 |
| 8037380 | Verifying data integrity of a non-volatile memory system during data caching process To ensure integrity of non-volatile flash, the controller programs the non-volatile memories with background test patterns and verifies the non-volatile memories during power on self test (POST) operation. In conjunction with verifying the non-volatile memories, the... | 10/11/2011 |
| 8037293 | Selecting a random processor to boot on a multiprocessor system Pervasive logic is provided that includes a random event generator. The random event generator randomly selects which processor of a plurality of processors in the multiprocessor system is to be a boot processor for the multiprocessor system. A corresponding configu... | 10/11/2011 |
| 8024773 | Integrated guidance and validation policy based zoning mechanism A mechanism is provided to automatically retrieve zoning best practices from a centralized repository and to ensure that automatically generated zones do not violate these best practices. A user selects a set of hosts and storage controllers. The user also selects a... | 09/20/2011 |
| 8024574 | Unidirectional message masking and validation system and method A system for secure communication is provided. A random value generator is configured to generate a random value. A message validation code generator is coupled to the random value generator and configured to generate a message validation code based on a predetermin... | 09/20/2011 |
| 8019078 | Phone call mute notification A phone call mute notification applies an aural effect to the user's speech, other parties' speech, non-speech, or combinations thereof. The phone call mute notification does not render speech unintelligible and may provide a constant indication that the phone call ... | 09/13/2011 |
| 8015379 | Wake-and-go mechanism with exclusive system bus response A wake-and-go mechanism is configured to issue a look-ahead load command on a system bus to read a data value from a target address and perform a comparison operation to determine whether the data value at the target address indicates that an event for which a threa... | 09/06/2011 |
