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| Number | Title | Issue Date |
| 7435990 | Arrangement for testing semiconductor chips while incorporated on a semiconductor wafer An arrangement that will provide multiple communication paths for the simultaneously testing of a plurality of un-diced chips on a semiconductor wafer that will simultaneously permit each such communication path to service more than one chip while using a minimum nu... | 10/14/2008 |
| 7381986 | Arrangement for testing semiconductor chips while incorporated on a semiconductor wafer An arrangement that will provide multiple communication paths for the simultaneously testing of a plurality of un-diced chips on a semiconductor wafer that will simultaneously permit each such communication path to service more than one chip while using a minimum nu... | 06/03/2008 |
| 7239376 | Method and apparatus for correcting gravitational sag in photomasks used in the production of electronic devices In a projection apparatus for projecting optical images, an optical mask support stage having a pair of separated arms. Each arm being provided with a respective mask chucking bar that supports a respective edge of a thin glass mask and applies to the respective edg... | 07/03/2007 |
| 7234099 | High reliability memory module with a fault tolerant address and command bus A high reliability dual inline memory module with a fault tolerant address and command bus for use in a server. The memory module is a card approximately 151.35 mm or 5.97 inches long provided with about a plurality of contacts of which some are redundant, a plurali... | 06/19/2007 |
| 7026806 | Apparatus for preventing cross talk and interference in semiconductor devices during test An apparatus and a method for testing semiconductor devices such as integrated circuits having a handler for picking up an integrated circuit to be tested and placing the picked up integrated circuit into an automatic circuit test apparatus. When the circuit to be t... | 04/11/2006 |
| 7017095 | Functional pattern logic diagnostic method A method of diagnosing semiconductor device functional testing failures by combining deterministic and functional testing to create a new test pattern based on the functional failure by determining the location of and type of error in the failing circuit. This is ac... | 03/21/2006 |
| 6921288 | Semiconductor test and burn-in apparatus provided with a high current power connector for combining power planes A semi-conductor module burn-in test apparatus having a plurality burn-in boards each of which is provided a plurality of module test sockets thereon and each test socket is coupled to an adjacent test socket by with a high current, open/short split power connector ... | 07/26/2005 |
| 6909274 | Signal pin tester for AC defects in integrated circuits A test apparatus and a method for testing an integrated circuit's data storage device's input/output signal pins for alternating current (AC) defects, by providing an interface that will couple each respective individual test contact, in a subset of said contacts, t... | 06/21/2005 |
| 5457071 | Stackable vertical thin package/plastic molded lead-on-chip memory cube This is a semiconductor chip package configuration particularly suited for stacking. These described arrangement is especially adapted to be used with the so-called Lead-On-Chip type package. Each package is of minimum size, and provided with a thermal he... | 10/10/1995 |
| 5410409 | Search routine for ellipsometers A method of locating a predetermined variation in the surface of a film such as selected depression or elevation on a film deposited on a surface and for measuring the depth of the depression or height of the elevation comprising the steps of establishing... | 04/25/1995 |
| 5384546 | Time domain component multiplexor An integrated circuit in which closer matching or tracking of critical components, both active and passive, is achieved by time domain multiplexing of these critical components. Time domain multiplexing means that each of the components to be matched is a... | 01/24/1995 |
| 5227995 | High density semiconductor memory module using split finger lead frame The semiconductor memory module comprises a housing of plastic or ceramic in which two chips are stacked together back-to-back. The pads of the chips are electrically connected by wire bonding to beam leads which comprise outer bond leads, generally arran... | 07/13/1993 |
| 5207548 | Wafer transfer apparatus An apparatus (2) for transferring wafers between carriers of different densities having a loading station and unloading station; a lift for raising the wafers to be transferred into a wafer handler secured to a support. The wafer handler has two substanti... | 05/04/1993 |
| 5166888 | Fabrication of particle beam masks A method for automatically splitting a layout of a hole pattern into two complementary arrangements for x-ray, electron beam, ion beams, i.e., particle beam masks. The method determines all inside and outside corners of said pattern and determining a stab... | 11/24/1992 |
| 5164818 | Removable VLSI assembly A system for mounting VLSI devices on a substrate is disclosed, offering a high contact density. Each package consists of a semiconductor device having protruding elongated contact pin (2) on its surface and a wiring substrate having a cavity (3) on its s... | 11/17/1992 |
| 5151559 | Planarized thin film surface covered wire bonded semiconductor package This is a semiconductor chip in which the conductive path between the chip and the lead frame via wires can be easily and reproduceably improved. This is accomplished by improving the bond between the wires and the lead frame members to which the wires ar... | 09/29/1992 |
| 5093584 | Self calibrating timing circuit A clock circuit, together with a control current generator and a ratio circuit coupled thereto. The ratio circuit, of the invention, utilizes at least two capacitors each of which is coupled in series with a respective transistor and arranged in parallel ... | 03/03/1992 |
| 5086018 | Method of making a planarized thin film covered wire bonded semiconductor package A method of making a semiconductor chip in which the conductive path between the chip and the lead frame via wires can be easily and reproduceably improved. This is accomplished by improving the bond between the wires and the lead frame members to which t... | 02/04/1992 |
| 5078581 | Cascade compressor The compressor cascade comprises a plurality of tandem-connected membrane pumps, each of the pumps having a plurality of stroke chambers whose volumes decrease in the direction of the fluid flow through the pumps. Each chamber has several parallel-connect... | 01/07/1992 |
| 5075621 | Capacitor power probe A probe for testing integrated circuit wafers is disclosed herein. The probe comprises a ceramic body having an extended voltage contact on the upper most surface, an extended ground contact on the lower most surface, sets of interdigitated internal metal... | 12/24/1991 |
| 5063300 | Method and apparatus for determining line centers in a microminiature element Method and an apparatus for determining line centers in a microminiature element such as on a semiconductor wafer or a mask having linewidths and other spacings below the one micron range. The invention uses, two focussed laser beams which are directed ac... | 11/05/1991 |
| 5043674 | Differential receiver with high common-mode range This describes a differential amplifier for producing an output current proportional to the differential input voltage regardless of the common-mode input voltage and comprises two identical voltage networks coupled between differential voltage inputs and... | 08/27/1991 |
| 4996587 | Integrated semiconductor chip package A semiconductor package utilizing a carrier with substantially parallel top and bottom surfaces having a recess in the bottom surface and a slot in the top surface communicating with the recess in the bottom surface and provided with electrical conductors... | 02/26/1991 |
| 4967104 | Circuit for increasing the output impedance of an amplifier The present invention teaches an arrangement for increasing the output impedance of a power amplifier coupled to a capacitively loaded line during the switching of power levels by the amplifier on the line. The arrangement of the invention reduces undesir... | 10/30/1990 |
| 4965654 | Semiconductor package with ground plane A plastic encapsulated semiconductor package in which the connecting lead frame members are deposited over the surface of the device together with a covering ground plane so as to provide enhanced electrical and thermal coupling of the members and the dev... | 10/23/1990 |
| 4929301 | Anisotropic etching method and etchant The present invention is directed toward an improved etching solution which is a five component system and does not use ethylene-diamine. This etch will preferentially etch lightly doped, single crystalline silicon at an etch rate of 0.6 microns per minut... | 05/29/1990 |
| 4916519 | Semiconductor package In an encapsulated semiconductor module in which a semiconductor chip, having a major surface with terminals thereon, is deposed within the encapsulating material, a plurality of self-supporting, unitary, discrete, and continuous lead frame conductors for... | 04/10/1990 |
| 4912547 | Tape bonded semiconductor device Multiple, single conductor, tape automated bonding (TAB) tapes are sequentially applied to a semiconductor device by the bonding of a first, etched, single layer TAB tape to an outer row of bonding pads on a semiconductor chip and to selected contacts on ... | 03/27/1990 |
| 4896054 | Optional single or double clocked latch This is related to a logic circuit which requires a double clocking latch during testing of the circuit to prevent race or flushing of the scan rings from occuring during the test mode and yet can be operated to capture and hold output data during the ope... | 01/23/1990 |
| 4876114 | Process for the self fractionation deposition of a metallic layer on a workpiece A process for the evaporation deposition of a layer of metal on a workpiece is described in which a charge of a metal is placed in a crucible formed of a material having a vapor pressure lower than the vapor pressure of the metal at a selected temperature... | 10/24/1989 |
| 4861425 | Lift-off process for terminal metals A process is described for selective removal of unwanted metallization from the surface of a semiconductor device. The process comprises the usual deposition of a configurable image defining layer on the surface of the device upon which a suitable pad lim... | 08/29/1989 |
| 4833421 | Fast one out of many differential multiplexer This is a one of the many differential multiplier circuits providing a fast selection of a one set of differential input signals from a multiplexity of differential input signals in which a plurality of differential input circuits coupled to differential ... | 05/23/1989 |
| 4791261 | Crucible for evaporation of metallic film An evaporation source for RF heated evaporators in which the crucible has a susceptor made of a solid block of graphite carbon having a volume commensurate with the volume of molten material prior to evaporation. Moreover, the crucible has a depth that is... | 12/13/1988 |
| 4727267 | Clocked buffer circuit The present invention is especially directed towards an improved clocked buffer circuit that will clock, decode, repeat and invert an input signal. The clocked buffer circuit uses a clocked latch coupled to a decode circuit such that not only will the app... | 02/23/1988 |
| 4720822 | High frequency signal measurement method and apparatus This is an apparatus for and a method of measuring the time coherence of high frequency signals fed into different points along a high frequency transmission line regardless of where the input signal enters the line or what the propagation delay of the li... | 01/19/1988 |
| 4707667 | Offset corrected amplifier An amplifier circuit having offset voltage and offset voltage drift corrections which does not require resistive feedback and is suitable for use with unmatched high frequency field effect transistor circuits. The described circuit cancels the offset volt... | 11/17/1987 |
| 4697099 | Open line detector circuit This describes an open detector circuit essentially composed of comparator circuits with their outputs coupled to each other and to an open collector driver stage, driven from the output of the comparators. The detector circuit compares the voltages, such... | 09/29/1987 |
| 4686462 | Fast recovery power supply A tester for logic circuits provided with a fast recovery power supply for supplying high current to a logic circuit under test and for measuring a low current of the circuit under test. The power supply of the tester has first and second amplifiers coupl... | 08/11/1987 |
| 4681442 | Method for surface testing This teaches a method and device for testing of the surface of a transparent object such as a photolithographic mask in which respective recordings with darkfield reflection illumination and darkfield transmission illumination is made, and the intensities... | 07/21/1987 |
| 4659585 | Planarized ceramic substrates A method of planarizing or smoothing the surface of a ceramic substrate by deposition of a silicon nitride layer. The silicon nitride in addition to planarizing the surface forms an alpha particle barrier. The substrates suitable for planarization with si... | 04/21/1987 |
