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| Number | Title | Issue Date |
| 7944034 | Array molded package-on-package having redistribution lines A semiconductor device with a sheet-like insulating substrate (101) integral with two or more patterned layers of conductive lines and vias, a chip attached to an assembly site, and contact pads (103) in pad locations has an encapsulated region on the ... | 05/17/2011 |
| 7943499 | FUSI integration method using SOG as a sacrificial planarization layer A method for making a transistor 20 that includes using a transition metal nitride layer 200 and/or a SOG layer 220 to protect the source/drain regions 60 from silicidation during the silicidation of the gate electrode 90. The SOG ... | 05/17/2011 |
| 7943479 | Integration of high-k metal gate stack into direct silicon bonding (DSB) hybrid orientation technology (HOT) pMOS process flow A method for semiconductor processing provides a DSB semiconductor body having a first crystal orientation layer, and a second crystal orientation layer, and a border region disposed between the first and second crystal orientations. A high-k metal gate stack is dep... | 05/17/2011 |
| 7943472 | CoSi2 Schottky diode integration in BiSMOS process Cobalt silicide (CoSi2) Schottky diodes fabricated per the current art suffer from excess leakage currents in reverse bias. In this invention, an floating p-type region encircles each anode of a CoSi2 Schottky diode comprising of one or more CoSi2 anodes. The result... | 05/17/2011 |
| 7943456 | Selective wet etch process for CMOS ICs having embedded strain inducing regions and integrated circuits therefrom A method for fabricating a CMOS integrated circuit (IC) and ICs therefrom includes providing a substrate having a semiconductor surface including PMOS regions for PMOS devices and NMOS regions for NMOS devices. A gate stack including a gate electrode layer is formed... | 05/17/2011 |
| 7595649 | Method to accurately estimate the source and drain resistance of a MOSFET Measurements of parameters of MOS transistors, also known as MOSFETs, such as threshold potentials, require accurate estimates of source and drain series resistance. In cases where connections to the MOSFET include significant external series resistance, as occurs i... | 09/29/2009 |
| 7595644 | Power-over-ethernet isolation loss detector An AC generator has a first terminal coupled through an Isolation Loss Detect (ILD) capacitor to the positive bus of a Power-Over-Ethernet (POE) system, and has a second terminal coupled through the primary of a transformer to earth ground. AC current flowing betwee... | 09/29/2009 |
| 7595624 | Slope compensation for switching regulator In one embodiment, a switching regulator comprises a control circuit that activates and deactivates at least one power switch to control a voltage of a switching node. The system also comprises an inductor that conducts a current from the switching node to an output... | 09/29/2009 |
| 7595619 | Feed-forward circuit for adjustable output voltage controller circuits A feedback loop in a variable power supply has an adjustable response speed based on operating conditions of the power supply. The response speed can be increased upon encountering a transient to improve response performance to the transient. A response speed contro... | 09/29/2009 |
| 7595616 | Control circuit for a polarity inverting buck-boost DC-DC converter A control circuit for a polarity inverting buck-boost DC-DC converter, includes an operational trans-conductance amplifier that has inputs to which a sensed voltage difference signal is applied and an output connected to an input of a voltage-to-duty-cycle converter... | 09/29/2009 |
| 7595615 | Systems and methods for providing over-current protection in a switching power supply A system and method is provided for providing integrated over-current protection in a switching power supply. In one embodiment, a switching power supply could comprise a gate drive circuit operative to receive a pulse-width modulated (PWM) signal and to drive at le... | 09/29/2009 |
| 7595525 | Integrated circuit capacitor having antireflective dielectric A capacitor (100) is disclosed that is formed as part of an integrated circuit (IC) fabrication process. The capacitor (100) has conductive top and bottom electrodes (140, 144) and a nonconductive capacitor dielectric (142). In one exampl... | 09/29/2009 |
| 7595245 | Semiconductor device having a gate electrode material feature located adjacent a gate width side of its gate electrode and a method of manufacture therefor The present invention provides a semiconductor device, a method of manufacture therefore and an integrated circuit including the same. The semiconductor device (300), without limitation, may include a gate electrode (320) having a gate length (l) and a... | 09/29/2009 |
| 7594162 | Viterbi pretraceback for partial cascade processing This invention modifies Viterbi decoding to improve BER. Within the state metric unit cascade block, this invention forces the unused ACS units decision bits to a 0 for the top rail and a 1 for the bottom rail. This invention modifies the final maximum state index w... | 09/22/2009 |
| 7593841 | Emulation export sequence with distributed control Emulation information including emulation control information and emulation data is exported from a data processor by arranging the emulation information into information blocks, and outputting a sequence of the information blocks from the data processor. Some of th... | 09/22/2009 |
| 7593580 | Video encoding using parallel processors A digital video acquisition system including a plurality of image processors (30A; 30B) is disclosed. A CCD imager (22) presents video image data on a bus (video_in) in the form of digital video data, arranged in a sequence of frames. A master i... | 09/22/2009 |
| 7592867 | Common mode feedback for large output swing and low differential error A differential amplifier includes a differential input pair (2A) coupled to a folded cascode stage (2B) and a common mode feedback circuit (34) including a tracking circuit (30A) coupled to first (Vout−) and second (Vout... | 09/22/2009 |
| 7592860 | Minimizing the number of external terminals required when compensation is to be provided for signal drop in bond wire of a package in which an integrated circuit is provided Compensation is provided for signal drop in bond wires of an integrated circuit (IC) while minimizing the number of external terminals in the IC package. A functional circuit provides an output signal (e.g., voltage) on a pad of the IC, which is connected to an exte... | 09/22/2009 |
| 7592859 | Apparatus to compare an input voltage with a threshold voltage Apparatus to compare an input signal to a threshold level are disclosed. An example circuit described herein includes a Widlar bandgap circuit to receive the input signal, an intermediate stage coupled with the output of the Widlar bandgap circuit, and a final stage... | 09/22/2009 |
| 7590974 | Recovery from corruption using event offset format in data trace A method of tracing data processor activity with recover from detection of trace stream corruption. If the first trace data following detection of corruption is not a program counter sync point, then the trace transmits an indication of the current program counter a... | 09/15/2009 |
| 7590912 | Using a chip as a simulation engine The chip is placed in self simulation mode. When the trace logic does not have any more data to output it changes the state of the advance signal. The clock generator detects this state change and issues one gated clock to the functional logic. This creates a new CP... | 09/15/2009 |
| 7590910 | Tap and linking module for scan access of multiple cores with IEEE 1149.1 test access ports An architecture for testing a plurality of circuits on an integrated circuit is described. The architecture includes a TAP Linking Module located between test pins on the integrated circuit and 1149.1 Test Access Ports (TAP) of the plurality of circuits to be tested... | 09/15/2009 |
| 7590894 | Method of translating system events into signals for activity monitoring Disclosed herein is a system and method for receiving encoded events from a system that is being debugged or profiled. The encoded events are input to a decoder in order to decode the encoded events, wherein the decoder is configured to selectively adjust the bandwi... | 09/15/2009 |
| 7590893 | Recording control point in trace receivers A trace receiver with multiple recording interfaces may be used to record the same input. The historical control point for starting and stopping trace recording is placed very near the front end. A new control point further from the front end allows the front end to... | 09/15/2009 |
| 7590892 | Method and system of profiling real-time streaming channels A method and system of profiling streaming channels. At least some of the illustrative embodiments are methods comprising executing a traced program on a target system (the traced operating on a plurality of streaming channels), obtaining values indicative of which ... | 09/15/2009 |
| 7590677 | Processor with summation instruction using overflow counter Performing a sum of numbers operation in a variable bit-length environment of a processor in response to a summation instruction, comprising a) adding a least significant portion (LSP) of a first number to a LSP of another number from a plurality of numbers, wherein... | 09/15/2009 |
| 7590047 | Memory optimization packet loss concealment in a voice over packet network A method to reduce memory requirements for a packet loss concealment algorithm in the event of packet loss in a receiver of pulse code modulated voice signals. A voice playout unit in the receiver shares its nominal delay buffer with a history buffer of a packet los... | 09/15/2009 |
| 7589533 | One time operating state detecting method and apparatus A method and apparatus for detecting a change in an electrical property between contacts. A one-time operating state detection device includes a member coupling a pair of contacts and a detector for detecting a change in the coupling between the pair of contacts whe... | 09/15/2009 |
| 7589516 | Poly-phase electric energy meter A poly-phase electric energy meter comprises a front-end that converts analog current input signals and analog voltage input signals to digital current and voltage samples and a micro-controller for computing power consumed. The front end includes first and second i... | 09/15/2009 |
| 7589378 | Power LDMOS transistor A laterally diffused metal-oxide-semiconductor transistor device includes a substrate having a first conductivity type with a semiconductor layer formed over the substrate. A source region and a drain extension region of the first conductivity type are formed in the... | 09/15/2009 |
| 7587757 | Surveillance implementation in managed VOP networks A procedure for accomplishing surveillance within a managed VoP network when end-user encryption/decryption and NAT are in place. The procedure comprises first analyzing the network from call signaling and message standpoints, leading to the identification of suitab... | 09/08/2009 |
| 7587648 | Integrated circuit having electrically isolatable test circuitry Special test circuitry in an IC for wafer level testing selectively connects the specialized test circuitry to the functional circuitry during wafer test. Following wafer test the special test circuitry is electrically isolated from the functional circuitry and powe... | 09/08/2009 |
| 7587644 | Scan testing using response pattern as stimulus pattern after reset Scan testing of plural target electrical circuits, such as circuits 1 through N, becomes accelerated by using the scan test response data output from one circuit, such as circuit 1, as the scan test stimulus data for another circuit, such as circuit | 09/08/2009 |
| 7587642 | System and method for performing concurrent mixed signal testing on a single processor The present application describes a system and method for testing semiconductor devices and specifically for testing mixed signal semiconductor devices. The test systems are configured to test the semiconductor devices using overlapping test setups by configuring va... | 09/08/2009 |
| 7587583 | Method and system for processing a “WIDE” opcode when it is not used as a prefix for an immediately following opcode Methods and systems are provided for the selective use of a Java WIDE opcode as a prefix as defined in the instruction set of the Java virtual machine or performing a task assigned to the Java WIDE opcode. A Java WIDE opcode is fetched, a determination is made as to... | 09/08/2009 |
| 7587577 | Pipelined access by FFT and filter units in co-processor and system bus slave to memory blocks via switch coupling based on control register content A system architecture including a co-processor and a memory switch resource is disclosed. The memory switch includes multiple memory blocks and switch circuitry for selectably coupling processing units of the co-processor, and also a bus slave circuit coupled to a s... | 09/08/2009 |
| 7587539 | Methods of inter-integrated circuit addressing and devices for performing the same Inter-integrated circuit-capable devices for use on an inter-integrated circuit bus are disclosed. The inter-integrated circuit-capable devices include integrated, internally-configurable addressing registers in place of external pins. Cascaded systems of inter-inte... | 09/08/2009 |
| 7587532 | Full/selector output from one of plural flag generation count outputs A method and apparatus for adaptive buffer sizing adjusts the size of the buffer at different levels using a “high water mark” to different levels for different system conditions. The high water mark is used by the buffer logic as an indication of when to assert... | 09/08/2009 |
| 7587525 | Power control with standby, wait, idle, and wakeup signals An apparatus and method for conserving power in a memory information transfer system. The system may include a direct memory access (DMA) controller coupled to a memory storage device and a peripheral device. The DMA controller transfers information from the memory ... | 09/08/2009 |
| 7587315 | Concealment of frame erasures and method A decoder for code excited LP encoded frames with both adaptive and fixed codebooks; erased frame concealment uses repetitive excitation plus a smoothing of pitch gain in the next good frame, plus multilevel voicing classification with multiple thresholds of correla... | 09/08/2009 |
