Bizarre Patents
A beach chair which can be adapted for a woman who is pregnant and wishes to sunbathe in the prone position.
PatentStorm News
Make the Most of Our Site
See this month's Top Inventors and Most Cited Patents.
Stay on top of the latest innovations by subscribing to an RSS feed.
Registered users: Manage your profile.
| Number | Title | Issue Date |
| 8093622 | Semiconductor device and its driving method A semiconductor device having a thyristor SCR with reduced turn-off time. A third semiconductor region of the second conductivity type (anode AN) and a fourth semiconductor region of the first conductivity type (anode gate AG) are formed in the top layer of a first ... | 01/10/2012 |
| 8093070 | Method for leakage reduction in fabrication of high-density FRAM arrays A method is provided for fabricating a ferroelectric capacitor structure including a method for etching and cleaning patterned ferroelectric capacitor structures in a semiconductor device. The method comprises etching portions of an upper electrode, etching ferroele... | 01/10/2012 |
| 8088664 | Method of manufacturing integrated deep and shallow trench isolation structures A method of forming an integrated deep and shallow trench isolation structure comprises depositing a hard mask on a film stack having a plurality of layers formed on a substrate such that the hard mask is deposited on a furthermost layer from the substrate, imprinti... | 01/03/2012 |
| 8085958 | Virtualizer sweet spot expansion Audio loudspeaker virtualizers and cross-talk cancellers and methods use a combination of interaural intensity difference and interaural time difference to define virtualizing filters. This allows enlargement of a listener's sweet spot based on psychoacoustic effect... | 12/27/2011 |
| 8085951 | Method and system for determining a gain reduction parameter level for loudspeaker equalization Methods, digital systems, and computer readable media are provided for determining a gain reduction parameter level for loudspeaker equalization by determining a noise score, an equalization effectiveness score, and an equalization non-effectiveness score for a cand... | 12/27/2011 |
| 8085940 | Rebalancing of audio Rebalancing of an audio signal refers to achieving a balance of perceived loudness, typically of right and left channels, given an unbalanced input. A flexible method to automatically rebalance an audio input signal is robust against noise in extreme cases through t... | 12/27/2011 |
| 8085580 | System for bitcell and column testing in SRAM A system comprises a storage cell coupled to multiple bitlines and a transistor that couples to the multiple bitlines in parallel with the storage cell. The transistor is activated while the storage cell is read. ... | 12/27/2011 |
| 8085074 | Fast-locking delay locked loop A fast locking delay-locked loop (DLL), which can also operate as a clock data recovery circuit (CDR), includes a delay chain, a sampling circuit and a transition detector. An input signal and delayed versions of the input signal generated by the delay chain are sam... | 12/27/2011 |
| 8085008 | System for accounting for switch impendances A Universal Serial Bus (USB) switch matrix is provided. The switch matrix generally comprises a switch network, and amplifier, a adjustable current source, and variable resistors. The switch network is able to output a differential output signal and a common mode si... | 12/27/2011 |
| 8084787 | PMD liner nitride films and fabrication methods for improved NMOS performance Semiconductor devices (102) and fabrication methods (10) are provided, in which a nitride film (130) is formed over NMOS transistors to impart a tensile stress in ail or a portion of the NMOS transistor to improve carrier mobility. The nitride l... | 12/27/2011 |
| 8084312 | Nitrogen based implants for defect reduction in strained silicon A transistor is fabricated upon a semiconductor substrate, where the yield strength or elasticity of the substrate is enhanced or otherwise adapted. A strain inducing layer is formed over the transistor to apply a strain thereto to alter transistor operating charact... | 12/27/2011 |
| 8081481 | Apparatus and method for a clip device for coupling a heat sink plate system with a burn-in board system A clip for coupling a first board and second board, the first board having plurality of first post coupled thereto, the second board having a plurality of second posts coupled thereto, each second post being a cylinder for receiving a first post, the first and secon... | 12/20/2011 |
| 8078927 | Wrapper leads gating TAP instruction and data registers In a first embodiment a TAP 318 of IEEE standard 1149.1 is allowed to commandeer control from a WSP 202 of IEEE standard P1500 such that the P1500 architecture, normally controlled by the WSP, is rendered controllable by the TAP. In a second embodiment... | 12/13/2011 |
| 8078898 | Synchronizing TAP controllers with sequence on TMS lead A method comprises a system comprising a host device coupled to a first remote device actively operating according to a state diagram that the host device and all remote devices follow during operation of the system. The method further comprises powering up a second... | 12/13/2011 |
| 8078897 | Power management in federated/distributed shared memory architecture This invention is a power management scheme for a shared memory multiprocessor system which splits the control logic between the master-specific logic and memory bank logic. Power-down is initiated from a central power-down controller. This central power-down contro... | 12/13/2011 |
| 8078842 | Removing local RAM size limitations when executing software code An electronic device that comprises a processor including an individual instruction and a first group of instructions. The device further comprises a memory externally coupled to the processor, as well as a second group of instructions. When executed, the first grou... | 12/13/2011 |
| 8073684 | Apparatus and method for automatic classification/identification of similar compressed audio files An audio file is divided into frames in the time domain and each frame is compressed, according to a psycho-acoustic algorithm, into file in the frequency domain. Each frame is divided into sub-bands and each sub-band is further divided into split sub-bands. The spe... | 12/06/2011 |
| 8073074 | System and method for power control in a wireless transmitter A power control loop includes a feed forward unit 301 coupled to a data source, the feed forward unit 301 processes a signal for transmission, a feedback unit 302 coupled to the feed forward unit 301, the feedback unit 302 generate... | 12/06/2011 |
| 8072918 | Network-based inter-cell power control for multi-channel wireless networks A method is described for operating a cellular network, where the cellular network uses a plurality of frequency division multiplexing (FDM) bands for wireless communication from user equipment (UE) to a base station (NodeB). At least one band-specific cell paramete... | 12/06/2011 |
| 8072770 | Semiconductor package with a mold material encapsulating a chip and a portion of a lead frame Various exemplary embodiments provide components, devices, and methods of semiconductor packaging. The disclosed packaging component can include a mold material disposed around a lead frame and at least an integrated circuit (IC), wherein the IC is electrically conn... | 12/06/2011 |
| 8071430 | Stress buffer layer for ferroelectric random access memory An F-RAM package having a semiconductor die containing F-RAM circuitry, a mold compound, and a stress buffer layer that is at least partially located between the semiconductor die and the mold compound. Also, a method for making an F-RAM package that includes provid... | 12/06/2011 |
| 8069290 | Processing system operable in various execution environments A processing system operable in various execution environments. The system comprises plural processor cores having respective interrupt inputs, respective wait for interrupt outputs, and respective security outputs. The system also comprises a register coupled to at... | 11/29/2011 |
| 8069201 | 8×8 transform and quantization Low complexity (16 bit arithmetic) video compression has 8×8 block with transforms using 8×8 integer matrices and quantization with look up table scalar plus constant right shift for all quantization steps. Inverse quantization also a look up table scalar plus rig... | 11/29/2011 |
| 8068871 | Systems and methods for time optimization for silencing wireless devices in coexistence networks Embodiments provide systems and methods to optimize the time when to transmit a silencing frame, and hence, improve the overall network throughput and avoid access point transmission rate fall-back mechanism having an avalanche effect during coexistence of dissimila... | 11/29/2011 |
| 8068466 | Transmission of multiple information elements in multiple channels A transmission of information from a secondary to a primary node occurs in a plurality of N logical time durations. The transmission from the secondary to primary node in a wireless network is performed by first receiving an allocation of M>1 reverse link channels f... | 11/29/2011 |
| 8068267 | Speckle reduction in display systems that employ coherent light sources Speckle effect in display system is reduced by utilizing the instability of phase-coherent light and the transmission of the instable phase-coherent light through a multi-mode optical fiber with a suitable length. ... | 11/29/2011 |
| 8068043 | Method and apparatus for video processing in context-adaptive binary arithmetic coding A method and apparatus of a digital signal processor for coding of a significant map. The method for coding of a significant map includes carrying out a scan of at least a portion of a block of transform coefficients; calculating runs of zeros of the scanned data; a... | 11/29/2011 |
| 8067955 | Preventing erroneous operation in a system where synchronized operation is required This invention is a method of operating a system having multiple finite state machines where each finite state machine generating a ready signal when its operation is complete. This invention senses the multiple ready signals and waits until all the finite state mac... | 11/29/2011 |
| 8067795 | Single poly EEPROM without separate control gate nor erase regions A single-poly EEPROM memory device comprises source and drain regions in a semiconductor body, a floating gate overlying a portion of the source and drain regions, which defines a source-to-floating gate capacitance and a drain-to-floating gate capacitance, wherein ... | 11/29/2011 |
| 8067792 | Memory device with memory cell including MuGFET and FIN capacitor One embodiment of the present invention relates to a memory cell. The memory cell includes a multi-gate field effect transistor associated with a first region of a semiconductor fin. The memory cell also includes a fin capacitor coupled to a drain of the multi-gate ... | 11/29/2011 |
| 8067279 | Application of different isolation schemes for logic and embedded memory The present invention facilitates semiconductor device fabrication by providing mechanisms for utilizing different isolation schemes within embedded memory and other logic portions of a device. The isolation mechanism of the embedded memory portion is improved relat... | 11/29/2011 |
| 8065578 | Inverted TCK access port selector selecting one of plural TAPs The disclosure describes a novel method and apparatuses for allowing a controller to select and access different types of access ports in a device. The selecting and accessing of the access ports is achieved using only the dedicated TDI, TMS, TCK, and TDO signal ter... | 11/22/2011 |
| 8065577 | Dual controllers for scan paths, distributors, and collectors Functional circuits and cores of circuits are tested on integrated circuits using scan paths. Using parallel scan distributor and collector circuits for these scan paths improves test access of circuits and cores embedded within ICs and reduces the IC's power consum... | 11/22/2011 |
| 8065506 | Application specific instruction set processor for digital radio processor receiving chain signal processing This invention is an application specific integrated processor to implement the complete fixed-rate DRX signal processing paths (FDRX) for a reconfigurable processor-based multi-mode 3G wireless application. This architecture is based on the baseline 16-bit RISC arc... | 11/22/2011 |
| 8065505 | Stall-free pipelined cache for statically scheduled and dispatched execution This invention provides flexible load latency to pipeline cache misses. A memory controller selects the output of one of a set of cascades inserted execute stages. This selection may be controlled by a latency field in a load instruction or by a latency specificatio... | 11/22/2011 |
| 8065140 | Method and system for determining predominant fundamental frequency Methods, digital systems, and computer readable media are provided for determining a predominant fundamental frequency of a frame of an audio signal by finding a maximum absolute signal value in history data for the frame, determining a number of bits for downshifti... | 11/22/2011 |
| 8064717 | Digital camera and method Deblurring of digital camera images by estimating the blur function from an image extracted from a video sequence taken about the time of an image capture. The extracted image is selected to be the sharpest of the images of the video sequence, and comparison of this... | 11/22/2011 |
| 8064611 | Uplink noise cancellation A system comprising audio logic adapted to convert captured sound into an audio signal. The system also comprises transmission logic which causes noise to be added to the audio signal. The system further comprises processing logic adapted to at least partially remov... | 11/22/2011 |
| 8064546 | Random access preamble detection for long term evolution wireless networks This invention is a method for preamble detection with estimation of UE timing advance (TA) and channel quality information (CQI) which uses a sliding window to detect the preamble and estimate user timing advance and channel quality information. The window length i... | 11/22/2011 |
| 8064279 | Structure and method for screening SRAMS An integrated circuit containing an SRAM that provides a switch to decouple the SRAM wordline voltage from the SRAM array voltage during screening and that also provides different wordline and array voltages during a portion of the SRAM bit screening test. A method ... | 11/22/2011 |
