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Apparatus for Simulating a High Five
A self-righting hand-arm configuration which is adapted to pivot when struck by a user, thereby simulating a "high five."
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| Number | Title | Issue Date |
| 6661465 | Television interface for handheld calculator for use with multiple calculator display formats An interface (10) for connecting a calculator (12) to a standard television (11), so that the calculator's display can be re-displayed on the television (1). The interface (10) is useful with different calculators having different display formats. Reforma... | 12/09/2003 |
| 6661900 | Digital graphic equalizer control system and method A digital graphic equalizer uses a predetermined number of equalizing bands each having a different center frequency, and the center frequencies span a predetermined audio bandwidth. For each equalizing band a minimum set of filters is provided. The filte... | 12/09/2003 |
| 6661683 | Charge pump having very low voltage ripple A charge pump circuit is configured for continuous control of the output of the charge pump circuit through continuous use of at least one charge pump capacitor coupled with a servo amplifier. During and between both phases of operation of the charge pump... | 12/09/2003 |
| 6661534 | Selective screening for printing files in a page description language This invention involves approximating a gray scale tone with a more limited range image producer, a process known as screening. This invention reduces the time needed for such screening by discriminating when screening is not needed. In a first embodiment... | 12/09/2003 |
| 6661517 | Shot averaging for fine pattern alignment with minimal throughput loss A way to average alignment measurements that obtains the advantage of multiple alignment marks per shot without requiring actual measurement of all alignment marks on all wafers of a batch. All alignment marks on all sampled shots are measured and average... | 12/09/2003 |
| 6661330 | Electrical fuse for semiconductor integrated circuits The present invention relates to a fuse and a method for forming a fuse over a semiconductor substrate. The fuse comprises forming a first contact member and a second contact member over a respective first region and a second region of a patterned, electr... | 12/09/2003 |
| 6661288 | Apparatus for effecting high speed switching of a communication signal An apparatus for effecting high speed switching of a communication signal between a first component and a second component includes: (a) a switching circuit configured for receiving the signal from the first component that includes a plurality of switch e... | 12/09/2003 |
| 6661266 | All digital built-in self-test circuit for phase-locked loops In general, a built-in self test circuit and method is provided that measures error in any periodic signal and, particularly, a Phase Lock Loop (PLL) output clock signal. The circuit includes a short-pulse generator that generates a short-pulse signal hav... | 12/09/2003 |
| 6661255 | Interface circuit An interface circuit for a printer to prevent transmission of an incorrect control signal when power is input into the printer. The interface circuit improves the stability of the printer at the initial state of the rise of power supply voltages, and prev... | 12/09/2003 |
| 6661216 | Apparatus and method for controlling startup of a precharged switching regulator An apparatus for presenting a regulated output at an output locus established at a precharge level includes: (a) an error indicator generating an error signal indicating difference between a reference signal and a sensed signal; (b) a pulse indicator coup... | 12/09/2003 |
| 6660989 | CMOS imager having asynchronous pixel readout in order of pixel illumination This CMOS imager represents illuminance in the time domain. Once per frame, each pixel outputs a pulse after a time proportional to the illuminance on that pixel. Therefore, the illuminance on that pixel is related to the time difference between its pulse... | 12/09/2003 |
| 6660650 | Selective aluminum plug formation and etchback process An embodiment of the instant invention is a method of fabricating an electronic device over a semiconductor substrate having an interconnecting structure comprised of aluminum, the method comprising the steps of: forming a conductive structure (layers 120... | 12/09/2003 |
| 6662291 | Synchronous DRAM System with control data A memory circuit (14) having features specifically adapted to permit the memory circuit (14) to serve as a video frame memory is disclosed. The memory circuit (14) contains a dynamic random access memory array (24) with buffers (18, 20) on input and outpu... | 12/09/2003 |
| 6657308 | Method for forming a self-aligned contact An improved method for forming a contact well for a semiconductor device (10) is disclosed. According to this method, a first insulator layer (24) comprising an insulating material is formed around a gate (20). A contact well filler (32) is then formed ad... | 12/02/2003 |
| 6656852 | Method for the selective removal of high-k dielectrics One aspect of the invention relates to a method of etching a high-k dielectric. The method involves removing an exposed portion of a high-k dielectric layer from a substrate by wet etching with a solution comprising water, a strong acid, an oxidizing agen... | 12/02/2003 |
| 6656811 | Carbide emitter mask etch stop Bipolar transistors and methods for fabricating bipolar transistors are disclosed wherein an emitter-base dielectric stack is formed between emitter and base structures, comprising a carbide layer situated between first and second oxide layers. The carbid... | 12/02/2003 |
| 6656768 | Flip-chip assembly of protected micromechanical devices A low-cost ceramic package, in land-grid array or ball-grid array configuration, for micromechanical components is fabricated by coating the whole integrated circuits wafer with a protective material, selectively etching the coating for solder ball attach... | 12/02/2003 |
| 6656748 | FeRAM capacitor post stack etch clean/repair The present invention is directed to a method of forming an FeRAM integrated circuit, which includes performing a capacitor stack etch to define the FeRAM capacitor. The method comprises etching a PZT ferroelectric layer with a high temperature BCl3 | 12/02/2003 |
| 6655002 | Microactuator for use in mass data storage devices, or the like, and method for making same A microactuator, or micromotor, (60) and method for making it are presented such that a symmetrical build up of material is performed on opposite sides of a substrate. This reduces mechanical stresses in the device. In its construction, respective layers ... | 12/02/2003 |
| 6658615 | IC with IP core and user-added scan register An integrated circuit carries an intellectual property core. The intellectual property core includes a test access port 39 with test data input leads 15, test data output leads 13, control leads 17 and an external register present, ERP lead 37. A scan reg... | 12/02/2003 |
| 6658578 | Microprocessors A processor (100) is provided that is a programmable fixed point digital signal processor (DSP) with variable instruction length, offering both high code density and easy programming. Architecture and instruction set are optimized for low power consumptio... | 12/02/2003 |
| 6658503 | Parallel transfer size calculation and annulment determination in transfer controller with hub and ports The transfer controller with hub and ports originally developed as a communication hub between the various locations of a global memory map within the DSP is described. Using the technique of this invention, parallel size calculation/write annulment decis... | 12/02/2003 |
| 6658385 | Method for transforming HMMs for speaker-independent recognition in a noisy environment On improved transformation method uses an initial set of Hidden Markov Models (HMMs) trained on a large amount of speech recorded in a low noise environment R to provide rich information on co-articulation and speaker variation and a smaller database in a... | 12/02/2003 |
| 6657999 | Link layer gateway computer for interconnecting ethernet and 1394 networks A network configuration (10) including a first network medium which is a 1394 network as well as a second network medium. Each of the first and second network media is coupled to a corresponding plurality of host-computers (H1 through H3 and H5 through H7... | 12/02/2003 |
| 6657997 | Transporting ABCD bits using RTP The transport of ABCD bits in a digital packet network is facilitated by the inclusion of the ABCD bits into the RTP header of the digital packets. The ABCD bits are first placed in the unused bits of the RTP header. Redundancy of the previous ABCD bits, ... | 12/02/2003 |
| 6657832 | Mechanically assisted restoring force support for micromachined membranes The present invention includes an integrated circuit switch including a membrane supported over a first conductor on a substrate, a conductive region on the membrane and connecting to the first conductor on the substrate, a pulldown electrode on the subst... | 12/02/2003 |
| 6657495 | Operational amplifier output stage and method A multi-stage differential amplifier with rail-to-rail input may utilize an output stage including first and second low-voltage rated transistors and first and second high-voltage transistors. The first low-voltage rated transistor and the first high-volt... | 12/02/2003 |
| 6657484 | System and method for decoupling capacitance for an integrated circuit chip A system and method for decoupling capacitance for an integrated chip includes a load coupled between a power supply line and a ground. A distributed resistive-capacitive (RC) filter is coupled between the power supply line and the ground in series with t... | 12/02/2003 |
| 6657311 | Heat dissipating flip-chip ball grid array A heat dissipating flip-chip Ball Grid Array (BGA) (10) including a substrate (12), a die (14), a first set of solder balls (16) coupling the die with the substrate, a thermal compound (20) attached to a backside of the die, a second set of solder balls (... | 12/02/2003 |
| 6657996 | Apparatus and method for improving voice quality by removing tandem codecs in a voice communication link A system and method for reducing or eliminating degradation in voice transmission quality resulting from repeated or sequential compression and decompression of voice packets over one or more packet networks. When a voice connection is established between... | 12/02/2003 |
| 6654819 | External direct memory access processor interface to centralized transaction processor An external direct memory access unit includes an event recognizer recognizing plural event types, a priority encoder selecting for service one recognized external event, a parameter memory storing service request parameters corresponding to each event ty... | 11/25/2003 |
| 6654834 | Method and apparatus for data transfer employing closed loop of memory nodes Data transfer between a master node (300) and plural memory nodes (301-308) follows a synchronous fixed latency loop bus (255). Each memory node includes bus interface (311-318) which passes command, write data, address and read data to a next memory node... | 11/25/2003 |
| 6654920 | LBIST controller circuits, systems, and methods with automated maximum scan channel length An integrated circuit (10) comprising combinational circuitry (13). The integrated circuit further comprises a plurality of scan channels (SC1 through SC4). Each of the plurality of scan channels comprises a number of scan elements (EC11 throug... | 11/25/2003 |
| 6653676 | Integrated circuit capacitor The present invention discloses a novel integrated circuit capacitor and a method of forming such a capacitor. The capacitor formation begins with a base electrode 18 adjacent an insulating region 26. This base electrode 18 can comprise either polysilicon... | 11/25/2003 |
| 6653681 | Additional capacitance for MIM capacitors with no additional processing Capacitance for MIM capacitors is increased by connecting another interdigitated pattern at the poly level in parallel with overlying patterns at the metal levels. The poly layout is optimized to maximize intralevel capacitive coupling through sidewall ni... | 11/25/2003 |
| 6653711 | Reducing fuse programming time for non-volatile storage of data Multiple fuse circuits are used associated with a corresponding number of bits forming a desired value which may need to be stored in a non-volatile storage. Assuming the desired value contains a first count number of zeros and a second count number of on... | 11/25/2003 |
| 6653717 | Enhancement in throughput and planarity during CMP using a dielectric stack containing an HDP oxide A semiconductor device and process for making the same are disclosed which use reticulated conductors and a width-selective planarizing interlevel dielectric (ILD) deposition process to improve planarity of an interconnect layer. Reticulated conductor 52 ... | 11/25/2003 |
| 6653895 | Gain-boost nulling amplifier for auto-zero circuit A nulling amplifier (52A) for an auto-zeroed amplifier includes a first differential stage including first (3) and second (16) input transistors and a second differential stage including first (18) and second (19) nulling transistors coupled to drains of ... | 11/25/2003 |
| 6654516 | Optical system and method Optical network dispersion compensation with adaptive dynamic optical filters which relate magnitude and phase of multichannel optical signals.... | 11/25/2003 |
| 6650191 | Low jitter ring oscillator architecture A low power and low jitter CMOS ring oscillator having a novel architecture that includes fully symmetrical differential current steering delay cells. This novel ring oscillator includes a first capacitor coupled between the first power supply rail and a ... | 11/18/2003 |
