Quotables
"To place a man in a multi-stage rocket and project him into the controlling gravitational field of the moon where the passengers can make scientific observations, perhaps land alive, and then return to earth--all that constitutes a wild dream worthy of Jules Verne. I am bold enough to say that such a man-made voyage will never occur regardless of all future advances."
Lee deForest, American radio pioneer ; 1957
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| Number | Title | Issue Date |
| 8054529 | System and method for displaying images System and method for simultaneous display of multiple images using a single light modulator array. A preferred embodiment comprises a light source that produces a light with desired spectral characteristics, a color filter optically coupled to the light source, and... | 11/08/2011 |
| 8054358 | Solid state image pickup device This invention improves linearity of a solid-state image pickup device beyond that of the prior art source follower to improve image quality. The image pickup device has plural pixels disposed in an array. Each pixel includes: a photodiode (PD); a transfer transisto... | 11/08/2011 |
| 8054103 | Synchronous clock multiplexing and output-enable A synchronous circuit for clock multiplexing and output-enable is implemented using a pair of logic gates and an output block. Select signals and enable signals with the corresponding logic sense are provided as inputs to the pair of logic gates, which generate resp... | 11/08/2011 |
| 8054057 | Low dropout regulator testing system and device A device for testing low dropout (LDO) regulator is disclosed. In one embodiment, a device for testing LDO regulators includes an absolute value measurement module for measuring absolute output voltages of the LDO regulators including a resistor scaling array for ge... | 11/08/2011 |
| 8053876 | Multi lead frame power package According to an embodiment of the invention, a system, operable to facilitate dissipation of thermal energy, includes a mold compound, a die, a first lead frame, and a second lead frame. The die is disposed within the mold compound, and in operation generates therma... | 11/08/2011 |
| 8053873 | IC having voltage regulated integrated Faraday shield An integrated circuit (IC) includes a substrate having a top semiconductor surface and a bottom surface, and integrated circuitry including an analog subcircuit and at least one digital subcircuit formed on the top semiconductor surface. A plurality of through subst... | 11/08/2011 |
| 8053349 | BGA package with traces for plating pads under the chip A semiconductor flip-chip ball grid array package (600) with one-metal-layered substrate. The sites (611) of a two-dimensional array become usable for attaching solder balls of the signal (non-common net assignment) I/O type to the substrate under the ... | 11/08/2011 |
| 8053324 | Method of manufacturing a semiconductor device having improved transistor performance In one aspect provides a method of manufacturing a semiconductor device having improved transistor performance. In one aspect, this improvement is achieved by conducting a pre-deposition spacer deposition process wherein a temperature of a bottom region of a furnace... | 11/08/2011 |
| 8053322 | Epitaxial deposition-based processes for reducing gate dielectric thinning at trench edges and integrated circuits therefrom A method of fabricating an integrated circuit (IC) and ICs therefrom including a plurality of Metal Oxide Semiconductor (MOS) transistors having reduced gate dielectric thinning and corner sharpening at the trench isolation/semiconductor edge for gate dielectric lay... | 11/08/2011 |
| 8053296 | Capacitor formed on a recrystallized polysilicon layer The present invention provides a semiconductor device, a method of manufacture therefor, and an integrated circuit including the semiconductor device. The semiconductor device, among other elements, includes a recrystallized polysilicon layer 148 located over... | 11/08/2011 |
| 8053285 | Thermally enhanced single inline package (SIP) In a method and system for fabricating a thermally enhanced semiconductor device (200, 300) is packaged as a through hole single inline package (SIP). A leadframe (210, 310, 410) having a die pad (220, 320, 420) to attach an IC die (230, 330 | 11/08/2011 |
| 8053256 | Variable thickness single mask etch process The present invention relates to a method of performing a variable film etch using a variable thickness photomask material. Essentially, a thickness of an adjustable film layer is measured and converted into a contour map of film thickness over a region of a semicon... | 11/08/2011 |
| 8053252 | Mitigation of edge degradation in ferroelectric memory devices through plasma etch clean A ferroelectric memory device is fabricated while mitigating edge degradation. A bottom electrode is formed over one or more semiconductor layers. A ferroelectric layer is formed over the bottom electrode. A top electrode is formed over the ferroelectric layer. The ... | 11/08/2011 |
| 8052286 | System and method for utilizing a scanning beam to display an image A method includes generating a plurality of beams that each illuminate a separate portion of a spatial light modulator. The spatial light modulator has a first dimension of a first length and a second dimension of a second length. Each of the beams spans a portion o... | 11/08/2011 |
| 8051399 | IC design flow incorporating optimal assumptions of power supply voltage drops at cells when performing timing analysis An aspect of the present invention selects a maximum voltage and a minimum voltage in respective sub-intervals of a timing window in which an output of a cell is expected to switch, and performing timing analysis based on the selected maximum voltage and the selecte... | 11/01/2011 |
| 8051398 | Test method and system for characterizing and/or refining an IC design cycle Systems and methods are provided for refining a design cycle for an integrated circuit. An integrated circuit design is generated. A plurality of non-critical paths within the integrated circuit design are identified. A set of at least one of the plurality of non-cr... | 11/01/2011 |
| 8051391 | Method for layout of random via arrays in the presence of strong pitch restrictions Exemplary embodiments provide a method for laying out an integrated circuit (“IC”) design and the IC design layout. In one embodiment, the IC design layout can include a first feature placed on a first intersecting point of a grid. The placed first feature can d... | 11/01/2011 |
| 8051351 | DDR circuit with addressable TAP linking circuitry and plural TAPS A process and apparatus provide a JTAG TAP controller (302) to access a JTAG TAP domain (106) of a device using a reduced pin count, high speed DDR interface (202). The access is accomplished by combining the separate TDI and TMS signals from th... | 11/01/2011 |
| 8051349 | Link instruction register with instruction register, and gate and multiplexer A test architecture accesses IP core test wrappers within an IC using a Link Instruction Register (LIR). An IEEE P1500 standard is in development for providing test access to these individual cores via a test structure called a wrapper. The wrapper resides at the bo... | 11/01/2011 |
| 8051347 | Scan-enabled method and system for testing a system-on-chip Scan-enabled method and system for testing a system-on-chip (SoC). The method includes electronically determining a slack in a signal at each port of a core of the SoC. The SoC includes multiple cores. Each core includes input ports and output ports. The method also... | 11/01/2011 |
| 8051313 | Apparatus, system and method of power state control An apparatus, system and method for asynchronously reducing power in a power domain. In one embodiment, the method includes: (1) receiving a sleep command for the power domain, (2) receiving, upon receiving the sleep command, an affirmative retention status signal d... | 11/01/2011 |
| 8051285 | Battery processor circuitry with separate public and private bus Systems and methods for providing a battery module 110 with secure identity information and authentication of the identity of the battery 110 by a host 120. In one embodiment, the system for providing a battery module with secure identity inform... | 11/01/2011 |
| 8050934 | Local pitch control based on seamless time scale modification and synchronized sampling rate conversion This invention locally controls the pitch of speech and audio signals. The invention is based on a seamless time scale modification (S-TSM) scheme connected to a synchronized sampling rate converter that switches between different time scale factors in a seamless ma... | 11/01/2011 |
| 8050903 | Apparatus and method for checkpointing simulation data in a simulator Apparatus for storing all logic simulation signal values generated by a logic simulator during a simulation run is provided. The apparatus includes a runtime array for storing a plurality of signal values for each time instance in a predetermined time period, and a ... | 11/01/2011 |
| 8050657 | Tamper resistant circuitry and portable electronic devices A portable electronic device. Tamper-resistant circuitry for inclusion in an electronic device. The tamper-resistant circuitry comprises wireless receiving circuitry operable to receive an incoming communication. The tamper-resistant circuitry also comprises a first... | 11/01/2011 |
| 8050641 | Limiting the power consumption of a wireless electronic system In at least some disclosed embodiments, a wireless electronic system includes a decoder module coupled to a processor. The decoder module is configured to send a signal to the processor based on a less than completely acquired burst of data. The less than completely... | 11/01/2011 |
| 8050375 | Digital phase locked loop with integer channel mitigation An embodiment of the present invention provides a phase locked loop that operates on clock signals derived from an RF clock signal generated by the phase locked loop. A frequency reference input provides a reference clock. A controllable oscillator generates the RF ... | 11/01/2011 |
| 8050368 | Nonlinear adaptive phase domain equalization for multilevel phase coded demodulators A novel and useful apparatus for and method of nonlinear adaptive phase domain equalization for multilevel phase coded demodulators. The invention improves the immunity of phase-modulated signals (PSK) to intersymbol interference (ISI) such as caused by transmitter ... | 11/01/2011 |
| 8050254 | IC reconstructing lost speech packets from secondary stage partial data A media over packet networking appliance provides a network interface, a voice transducer, and at least one integrated circuit assembly coupling the voice transducer to the network interface. The at least one integrated circuit assembly provides media over packet tr... | 11/01/2011 |
| 8050148 | Flash time stamp apparatus One embodiment of an apparatus for generating a time stamp includes a clock input, an event signal input and a time stamp output. A DLL is connected to the clock input, with a plurality of delay elements inside the DLL. An output of each of the delay elements is con... | 11/01/2011 |
| 8049946 | Lubricating micro-machined devices using fluorosurfactants A method of lubricating MEMS devices using fluorosurfactants 42. Micro-machined devices, such as a digital micro-mirror device (DMD™) 940, which make repeated contact between moving parts, require lubrication in order to prevent the onset of stiction... | 11/01/2011 |
| 8049654 | Digital trimming of SAR ADCs Successive approximation register (SAR) analog-to-digital converters (ADCs) generally employ capacitive digital-to-analog converters (CDACs) to perform data conversions. In these CDACs, matching of capacitive values is important, and for conventional high resolution... | 11/01/2011 |
| 8049562 | Amplifier with improved input resistance and controlled common mode An amplifier includes a first pair of transistors (the first pair) that defines a first output, each transistor of the first pair having a gate coupled to a first input terminal; a second pair of transistors (the second pair) that defines a second output, each trans... | 11/01/2011 |
| 8049555 | Low leakage sampling switch An electronic device includes a cascade of a plurality of transistors. Each transistor of the cascade receives an input voltage at a first terminal of its source/drain channel and receives a sampling clock signal at a control gate. The second terminal of the source/... | 11/01/2011 |
| 8049534 | Low-power high-speed differential driver with precision current steering In bipolar CMOS or BiCMOS process technologies, drivers (such as mixed mode or hybrid mode drivers) using both bipolar and CMOS transistors (i.e., field effect transistors or FETs) may have undesirable properties, such as reduced speed, ringing, latch-up, or lower e... | 11/01/2011 |
| 8049320 | Integrated circuit stacked package precursors and stacked packaged devices and systems therefrom A package-on-package (POP) package precursor and packaged devices and systems therefrom includes an electronic substrate including electrically conductive layers and a top surface. A first portion of the top surface has an IC die attached thereon. A second portion o... | 11/01/2011 |
| 8049312 | Semiconductor device package and method of assembly thereof A semiconductor die package includes: an assembly including a semiconductor die, a clip structure attached to an upper surface of the semiconductor die, and a heat sink attached to an upper surface of the clip structure; and a molding material partially encapsulatin... | 11/01/2011 |
| 8049254 | Semiconductor device with gate-undercutting recessed region A semiconductor device comprises a gate structure on a semiconductor substrate and a recessed region in the semiconductor substrate. The recessed region has a widest lateral opening that is near a top surface of the semiconductor substrate. The widest lateral openin... | 11/01/2011 |
| 8049214 | Degradation correction for finFET circuits A pair of split-gate fin field effect transistors (finFETs) in an IC, each containing a signal gate and a control gate, in which an adjustable voltage source, preferably in the form of a digital-to-analog-converter (DAC), is connected to the control gate of one of t... | 11/01/2011 |
| 8049119 | Integrated circuit package having integrated faraday shield A packaged integrated circuit (IC) (100) includes a first substrate (110) comprising a first plurality of layers and a first circuit coupling features (112) at an upper surface of the first substrate (110), the first plurality of layers i... | 11/01/2011 |
