Did You Know...
...that two musicians were responsible for the invention of color print film? Fascinated by photography, Leopold Godowsky and Leopold Mannes worked together to produce an easy-to-use, practical color film. They worked full time as music teachers and gave concerts while experimenting during their off hours in Mannes' kitchen. Their success earned them full-time, well-paying jobs at Kodak and their efforts resulted in Kodachrome film, which was introduced in 1935.
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| Number | Title | Issue Date |
| 8112737 | Contact resistance and capacitance for semiconductor devices A method generates a design layout for an integrated circuit. A design is provided for an integrated circuit. Library cells are selected according to the design. The library cells are mapped into a chip area map. Unmapped cells are filled with filler cells. Critical... | 02/07/2012 |
| 8112685 | Serial compressed data I/O in a parallel test compression architecture The disclosure describes novel methods and apparatuses for accessing test compression architectures (TCA) in a device using either a parallel or serial access technique. The serial access technique may be controlled by a device tester or by a JTAG controller. Furthe... | 02/07/2012 |
| 8112684 | Input linking circuitry connected to test mode select and enables IEEE 1149.1 Test Access Ports (TAPs) may be utilized at both IC and intellectual property core design levels. TAPs serve as serial communication ports for accessing a variety of embedded circuitry within ICs and cores including; IEEE 1149.1 boundary scan circuitry, ... | 02/07/2012 |
| 8112668 | Dynamic broadcast of configuration loads supporting multiple transfer formats A method for dynamically broadcasting configuration information to controllers connected in a scan topology in a target system is provided in which a selection event followed by the configuration information is received from a signal line at each of the controllers,... | 02/07/2012 |
| 8112652 | Multiprocessor system power management of shared memories powering down memory bank only when all processors indicate not powering that memory bank This invention manages power down and wakeup of shared memories in a multiprocessor system. A register for each shared memory has bits corresponding to each master. When a master wants to power down a memory, it sets its corresponding bit in the register. A hardware... | 02/07/2012 |
| 8112618 | Less-secure processors, integrated circuits, wireless communications apparatus, methods and processes of making An integrated circuit (122) includes an on-chip boot ROM (132) holding boot code, a non-volatile security identification element (140) having non-volatile information determining a less secure type or more secure type, and a processor (130 | 02/07/2012 |
| 8112400 | Method for collecting data from semiconductor equipment A method for collecting data from semiconductor equipment includes selecting a plurality of data values to request from semiconductor equipment and assigning each of the data values to a chamber. Each chamber is associated with an engine that processes the data valu... | 02/07/2012 |
| 8112168 | Process and method for a decoupled multi-parameter run-to-run controller A manufacturing process including a controller method to generate a tool setting which includes a tool offset and a device offset. The controller method uses a device parameter measurement to update the tool offset and device offset. A tool weight and a device weigh... | 02/07/2012 |
| 8112051 | Method and system for false frequency lock free autonomous scan in a receiver Method and system for false lock free autonomous scan in a receiver is disclosed. The method includes identifying a presence of a desired signal to avoid false frequency lock in a Frequency Modulation receiver. The method includes receiving a signal. The method furt... | 02/07/2012 |
| 8112050 | Reducing power consumption in receivers employing conversion to intermediate frequency A receiver to recover a signal of interest while consuming reduced power in some scenarios. The receiver contains a in-phase channel processing path and a quadrature phase channeling path for down converting an input signal to an intermediate frequency, and then rec... | 02/07/2012 |
| 8111760 | Deblocking filters Deblock filtering for Microsoft WMV video decoders partitions the computation so that the deblock filtering operations can be performed on horizontal or vertical stripes or in one pass on oversized macroblocks. ... | 02/07/2012 |
| 8111731 | Block scrambling for orthogonal frequency division multiple access A method of transmitting signals in a communication system over at least two time periods including generating a base signal comprising of at least two samples in each time period, selecting a scrambling sequence of length equal to or greater than the number of time... | 02/07/2012 |
| 8111330 | Method and apparatus for analog graphics sample clock frequency offset detection and verification A method and apparatus for an analog-to-digital video signal converter. The converter is controlled by a clock with controllable frequency and phase for sampling an analog signal. A circuit corrects the clock frequency using a period of a columnar frame differences ... | 02/07/2012 |
| 8111181 | Single-ended polar transmitting circuit with current salvaging and substantially constant bandwidth An embodiment of the invention provides a single-ended polar transmitting circuit. The single-ended polar transmitting circuit comprises a DAC, a differential-to-single-ended converter, a GmC filter and a load. The GmC filter comprises two gain stages, two filters, ... | 02/07/2012 |
| 8111098 | Segmented linear FM power amplifier Various apparatuses and methods for amplifying an FM signal in a segmented linear power amplifier are disclosed herein. For example, some embodiments provide an apparatus including a signal input, a signal output, and an output driver connected between the signal in... | 02/07/2012 |
| 8111092 | Register with process, supply voltage and temperature variation independent propagation delay path A digital data register is disclosed that provides setup and hold timing on the pre-register side, clock centering on the post-register side, and constant propagation delay time over variations in process, supply voltage and temperature (PVT) using a novel means to ... | 02/07/2012 |
| 8110857 | Low noise JFET A low noise (1/f) junction field effect transistor (JFET) is disclosed, wherein multiple implants push a conduction path of the transistor away from the surface of a layer upon which the transistor is formed. In this manner, current flow in the conduction path is le... | 02/07/2012 |
| 8110855 | Offset geometries for area reduction in memory arrays An array with cells that have adjacent similar structures that are displaced from each other across a common cell border in a direction that is not perpendicular to the cell border thus avoiding an across cell border design rule violation between the adjacent simila... | 02/07/2012 |
| 8110462 | Reduced finger end MOSFET breakdown voltage (BV) for electrostatic discharge (ESD) protection The present invention relates to electrostatic discharge (ESD) protection circuitry. Multiple techniques are presented to adjust one or more ends of one or more fingers of an ESD protection device so that the ends of the fingers have a reduced initial trigger or bre... | 02/07/2012 |
| 8110454 | Methods of forming drain extended transistors A transistor comprises a source region of a first conductivity type and electrically communicating with a first semiconductor region. The transistor also comprises a drain region of the first conductivity type and electrically communicating with a second semiconduct... | 02/07/2012 |
| 8110438 | Thermal method to control underfill flow in semiconductor devices A method and apparatus for assembling a semiconductor device. A chip (901) with solder bodies (903) on its contact pads is flipped onto a substrate (904). After the reflow process, a gap (910) spaces chip and substrate apart. A polymer pr... | 02/07/2012 |
| 8110416 | AC impedance spectroscopy testing of electrical parametric structures Defects in components in ICs which may cause circuit failures during operation of the IC are often difficult to detect during and immediately after fabrication of the IC by DC test methods. A method of testing components to detect such defects using AC Impedance Spe... | 02/07/2012 |
| 8110414 | Forming integrated circuit devices with metal-insulator-metal capacitors using selective etch of top electrodes A method of forming integrated circuits (IC) having at least one metal insulator metal (MIM) capacitor. A bottom electrode is formed on a predetermined region of a semiconductor surface of a substrate. At least one dielectric layer including silicon is formed on the... | 02/07/2012 |
| 8109485 | Tilting television wall mount A display wall mount comprising a wall bracket configured to couple to a wall and having a first wall bracket edge, a display bracket configured to couple to the display and having a first display bracket edge, and a curvilinear bar moveably coupled between the firs... | 02/07/2012 |
| 8108742 | Tap control of TCA scan clock and scan enable The disclosure describes novel methods and apparatuses for controlling a device's TCA circuit when the device exists in a JTAG daisy-chain arrangement with other devices. The methods and apparatuses allow the TCA test pattern set used during device manufacturing to ... | 01/31/2012 |
| 8108641 | Methods, apparatus, and systems for secure demand paging and other paging operations for processor devices A secure demand paging system (1020) includes a processor (1030) operable for executing instructions, an internal memory (1034) for a first page in a first virtual machine context, an external memory (1024) for a second page in a second v... | 01/31/2012 |
| 8107570 | Space time block coded transmit antenna diversity for WCDMA A mobile communication system is designed with an input circuit coupled to receive a first plurality of signals (rj(i+τj), i=0−N−1) during a first time (T0-T1) from an external source and coupled to receive a second plurality... | 01/31/2012 |
| 8107547 | Receivers for embedded ACK/NAK in CQI reference signals in wireless networks Within a wireless network, uplink control information (UCI) transmitted by user equipment is received by a base station. The UCI includes a least two elements, a first set of symbols produced using a first information element and a second set of symbols produced usi... | 01/31/2012 |
| 8107420 | Wireless communications system with cycling of unique cell bit sequences in station communications A wireless communication system (10). The system comprises transmitter circuitry (BST1) comprising circuitry for transmitting a plurality of frames to a receiver in a first cell (Cell 1). Each of the plurality of frames comprises a bit group ( | 01/31/2012 |
| 8102809 | Time-sharing of sounding resources This invention is a method for time-sharing sounding resources. This invention time-shares one sounding source across plural user equipment for different sub-frames. This invention uses different sounding periods which are periodic and either non-changing in time or... | 01/24/2012 |
| 8102187 | Localized calibration of programmable digital logic cells An integrated circuit (IC) includes self-calibrating programmable digital logic circuitry. The IC includes at least one programmable digital logic cell, wherein the first programmable digital logic cell provides (i) a plurality of different accessible circuit config... | 01/24/2012 |
| 8102038 | Semiconductor chip attach configuration having improved thermal characteristics A semiconductor chip 101 with surface 101b free of circuitry assembled on a metal carrier 102 by an attachment layer 103 with thickness 103a. Included in layer 103 are metal bodies 104 and an adhesive po... | 01/24/2012 |
| 8101476 | Stress memorization dielectric optimized for NMOS and PMOS A method for forming a tensile SiN stress layer for stress memorization enhancement of NMOS transistors with a high Si—H/N—H bond ratio that does not degrade PMOS transistors. A CMOS integrated circuit is processed through a NMOS source and drain implant but not... | 01/24/2012 |
| 8099658 | Reduced complexity Viterbi decoder A Viterbi decoder includes a branch metric unit, an add-compare select unit coupled to the branch metric unit, and a trace-back unit coupled to the add-compare select unit. The branch metric unit includes a branch metric computation unit coupled to a thresholder uni... | 01/17/2012 |
| 8099642 | Formatter selectively outputting scan stimulus data from scan response data The disclosure describes a novel method and apparatus for allowing response data output from the scan outputs of a circuit under test to be formatted and applied as stimulus data input to the scan inputs of the circuit under test. Also the disclosure described a nov... | 01/17/2012 |
| 8099641 | Multiplexer selecting STP clock signal with tap control outputs Connection circuitry couples scan test port (STP) circuitry to test access port (TAP) circuitry. The connection circuitry has inputs connected to scan circuitry control output leads from the TAP circuitry, a select input lead, and a clock input lead. The connection ... | 01/17/2012 |
| 8098745 | Random access structure for wireless networks Apparatus and methods for accessing a wireless telecommunications network by transmitting a random access signal. The random access signal includes a random access preamble signal selected from a set of random access preamble signals constructed by cyclically shift ... | 01/17/2012 |
| 8098091 | Method in the compensation of unlinearities in an amplifier, and uses of the method and the amplifier In a method and an amplifier for the compensation of unlinearities e.g. of the class D type, wherein an audio signal is pulse-width modulated, e.g. with a carrier wave signal in the form of a triangular signal to provide a pulse-width modulated small-signal, the so-... | 01/17/2012 |
| 8097964 | IC having TSV arrays with reduced TSV induced stress An integrated circuit (IC) includes a substrate having a top side having active circuitry thereon including a plurality of metal interconnect levels including a first metal interconnect level and a top metal interconnect level, and a bottom side. At least one TSV ar... | 01/17/2012 |
| 8095840 | Serial scan chain in a star configuration A method implemented to test a plurality of components coupled in a star configuration, each component having a test access port (TAP) controller. The method comprises performing a capture phase of a scan operation on all of the TAP controllers in the star configura... | 01/10/2012 |
