Quotables
"We live in a society exquisitely dependent on science and technology, in which hardly anyone knows anything about science and technology."
Carl Sagan
PatentStorm News
Make the Most of Our Site
See this month's Top Inventors and Most Cited Patents.
Stay on top of the latest innovations by subscribing to an RSS feed.
Registered users: Manage your profile.
| Number | Title | Issue Date |
| 7202094 | Process for locating, displaying, analyzing, and optionally monitoring potential transient defect sites in one or more integrated circuit chips of a semiconductor substrate A process which addresses the problem of transient defects comprises first processing one or more test chips on a substrate to reveal one or more potential transient defects during subsequent processing of all of the chips on the substrate; identifying the exact loc... | 04/10/2007 |
| 7071113 | Process for removal of photoresist mask used for making vias in low K carbon-doped silicon oxide dielectric material, and for removal of etch residues from formation of vias and removal of photoresist mask A process for removal of a photoresist mask used to etch openings in low k carbon-doped silicon oxide dielectric material of an integrated circuit structure, and for removing etch residues remaining from either the etching of the openings or removal of the resist ma... | 07/04/2006 |
| 7050160 | Process and apparatus for integrating sheet resistance measurements and reflectance measurements of a thin film in a common apparatus A process for measuring both the reflectance and sheet resistance of a thin film, such as a metal film or a doped semiconductor, in a common apparatus comprises: directing a beam of radiation from a radiation source on the common apparatus onto a portion of the surf... | 05/23/2006 |
| 7015168 | Low dielectric constant fluorine and carbon-containing silicon oxide dielectric material characterized by improved resistance to oxidation The invention provides a process for forming a low k fluorine and carbon-containing silicon oxide dielectric material by reacting with an oxidizing agent one or more silanes containing one or more organofluoro silanes having the formula SiR1R2R... | 03/21/2006 |
| 6977183 | Process for locating, displaying, analyzing, and optionally monitoring potential transient defect sites in one or more integrated circuit chips of a semiconductor substrate A process which addresses the problem of transient defects comprises first processing one or more test chips on a substrate to reveal one or more potential transient defects during subsequent processing of all of the chips on the substrate; identifying the exact loc... | 12/20/2005 |
| 6955937 | Carbon nanotube memory cell for integrated circuit structure with removable side spacers to permit access to memory cell and process for forming such memory cell A carbon nanotube memory cell for an integrated circuit wherein a chamber is constructed in a layer of a dielectric material such as silicon nitride down to a first electrical contact. This chamber is filled with polysilicon. A layer of a carbon nanotube mat or ribb... | 10/18/2005 |
| 6942265 | Apparatus comprising a flexible vacuum seal pad structure capable of retaining non-planar substrates thereto A flexible vacuum seal pad structure capable of, for example, sealingly securing a bowed substrate to a finger apparatus or “endeffector” used to robotically engage and/or move the substrate from one processing station to another, or capable of securing a wafer ... | 09/13/2005 |
| 6930056 | Plasma treatment of low dielectric constant dielectric material to form structures useful in formation of metal interconnects and/or filled vias for integrated circuit structure A process for forming an integrated circuit structure comprises forming a layer of low k dielectric material over a previously formed integrated circuit structure, and treating the upper surface of the layer of low k dielectric material with a plasma to form a layer... | 08/16/2005 |
| 6858195 | Process for forming a low dielectric constant fluorine and carbon-containing silicon oxide dielectric material The invention provides a process for forming a low k fluorine and carbon-containing silicon oxide dielectric material by reacting with an oxidizing agent one or more silanes that include one or more organofluoro silanes selected from: (a) an organofluoro silane cont... | 02/22/2005 |
| 6838379 | PROCESS FOR REDUCING IMPURITY LEVELS, STRESS, AND RESISTIVITY, AND INCREASING GRAIN SIZE OF COPPER FILLER IN TRENCHES AND VIAS OF INTEGRATED CIRCUIT STRUCTURES TO ENHANCE ELECTRICAL PERFORMANCE OF COPPER FILLER A process for forming copper metal interconnects and copper-filled vias in a dielectric layer on an integrated circuit structure wherein the impurity level of the copper-filled metal lines and copper-filled vias is lowered, resulting in an increase in the average gr... | 01/04/2005 |
| 6821812 | Structure and method for mounting a small sample in an opening in a larger substrate A process and structure for mounting a small sample in an opening in a larger substrate by using an intermediate size structure, wherein the small sample is mounted in a small opening in the intermediate size structure which then, in turn, is mounted in an intermedi... | 11/23/2004 |
| 6809824 | Alignment process for integrated circuit structures on semiconductor substrate using scatterometry measurements of latent images in spaced apart test fields on substrate A process for measuring alignment of latent images in a photoresist layer of an integrated circuit structure on a semiconductor substrate with a test pattern formed in a lower layer on the substrate comprises the steps of forming a test pattern in selected fields of... | 10/26/2004 |
| 6806551 | Fuse construction for integrated circuit structure having low dielectric constant dielectric material Fuses, and optionally metal pads, are formed over a layer of low k dielectric material structure having first openings lined with conductive barrier material and filled to form metal interconnects in the upper surface of the low k dielectric material. A dielectric l... | 10/19/2004 |
| 6800940 | Low k dielectric composite layer for integrated circuit structure which provides void-free low k dielectric material between metal lines while mitigating via poisoning A composite layer of low k silicon oxide dielectric material is formed on an oxide layer of an integrated circuit structure on a semiconductor substrate having closely spaced apart metal lines thereon. The composite layer of low k silicon oxide dielectric material e... | 10/05/2004 |
| 6794756 | Integrated circuit structure having low dielectric constant material and having silicon oxynitride caps over closely spaced apart metal lines A capping layer of an insulator such as silicon oxynitride is formed over horizontally closely spaced apart metal lines on an oxide layer of an integrated circuit structure formed on a semiconductor substrate. Low k silicon oxide dielectric material which exhibits v... | 09/21/2004 |
| 6790784 | Plasma treatment of low dielectric constant dielectric material to form structures useful in formation of metal interconnects and/or filled vias for intergrated circuit structure A process for forming an integrated circuit structure comprises forming a layer of low k dielectric material over a previously formed integrated circuit structure, and treating the upper surface of the layer of low k dielectric material with a plasma to form a layer... | 09/14/2004 |
| 6767692 | Process for inhibiting edge peeling of coating on semiconductor substrate during formation of integrated circuit structure thereon A photoresist-free and ARC-free lip on the periphery of the upper surface of a semiconductor substrate adjacent the end edge of the substrate is formed by the steps of: forming an ARC layer on one surface of a semiconductor substrate; chemically treating the ARC lay... | 07/27/2004 |
| 6759337 | Process for etching a controllable thickness of oxide on an integrated circuit structure on a semiconductor substrate using nitrogen plasma and plasma and an rf bias applied to the substrate A process for etching oxide is disclosed wherein a reproducibly accurate and uniform amount of silicon oxide can be removed from a surface of an oxide previously formed over a semiconductor substrate by exposing the oxide to a nitrogen plasma in an etch chamber whil... | 07/06/2004 |
| 6756674 | Low dielectric constant silicon oxide-based dielectric layer for integrated circuit structures having improved compatibility with via filler materials, and method of making same An integrated circuit structure is disclosed wherein the capacitance between nearby conductive portions may be lowered using carbon-containing low k silicon oxide dielectric material, without contributing to the problem of via poisoning, by careful control of the ca... | 06/29/2004 |
| 6722026 | Apparatus and method for removably adhering a semiconductor substrate to a substrate support A process and apparatus is disclosed capable of removably adhering a semiconductor substrate to a substrate support in a sub-atmospheric environment using a plurality of individual fibers, each mounted at one end adjacent the substrate support, and each having a loo... | 04/20/2004 |
| 6723653 | Process for reducing defects in copper-filled vias and/or trenches formed in porous low-k dielectric material Removal of rough edges in punctured or ruptured pores on the walls of an opening, such as a via and/or trench opening, in a layer of porous dielectric material, in an integrated circuit structure, is carried out to permit satisfactory lining of all exposed surfaces ... | 04/20/2004 |
| 6713394 | Process for planarization of integrated circuit structure which inhibits cracking of low dielectric constant dielectric material adjacent underlying raised structures A planarization process for an integrated circuit structure which inhibits or prevents cracking of low k dielectric material which comprises one of one or more layers of dielectric material formed over raised portions of the underlying integrated circuit structure. ... | 03/30/2004 |
| 6673721 | PROCESS FOR REMOVAL OF PHOTORESIST MASK USED FOR MAKING VIAS IN LOW K CARBON-DOPED SILICON OXIDE DIELECTRIC MATERIAL, AND FOR REMOVAL OF ETCH RESIDUES FROM FORMATION OF VIAS AND REMOVAL OF PHOTORESIST MASK A process for removal of a photoresist mask used to etch openings in low k carbon-doped silicon oxide dielectric material of an integrated circuit structure, and for removing etch residues remaining from either the etching of the openings or removal of th... | 01/06/2004 |
| 6649219 | Process for forming a low dielectric constant fluorine and carbon-containing silicon oxide dielectric material characterized by improved resistance to oxidation The invention provides a process for forming a low k fluorine and carbon-containing silicon oxide dielectric material by reacting with an oxidizing agent one or more silanes containing one or more organofluoro silanes having the formula SiR1 R | 11/18/2003 |
| 6613665 | Process for forming integrated circuit structure comprising layer of low k dielectric material having antireflective properties in an upper surface A process is disclosed for forming an integrated circuit structure characterized by formation of a combined dielectric layer and antireflective coating layer. The process comprises forming a layer of dielectric material over an integrated circuit structur... | 09/02/2003 |
| 6607967 | Process for forming planarized isolation trench in integrated circuit structure on semiconductor substrate A process is disclosed for planarizing a semiconductor substrate after filling isolation trenches in the substrate with dielectric material wherein the respective thicknesses of a liner layer of dielectric material blanket deposited over the upper surface... | 08/19/2003 |
| 6583026 | Process for forming a low k carbon-doped silicon oxide dielectric material on an integrated circuit structure A process for forming a low k carbon-doped silicon oxide dielectric material (lkc-dsodm) on an integrated circuit structure is characterized by improved planarity and good gap fill in high aspect ratio regions of the integrated circuit structure, as well ... | 06/24/2003 |
| 6572925 | Process for forming a low dielectric constant fluorine and carbon containing silicon oxide dielectric material A process is provided for forming a low k fluorine and carbon-containing silicon oxide dielectric material by reacting with an oxidizing agent one or more silanes including one or more organofluoro silanes characterized by the absence of aliphatic C--H bo... | 06/03/2003 |
| 6566244 | Process for improving mechanical strength of layers of low k dielectric material A process for selectively reinforcing portions of a low k dielectric material which comprises first forming a low k dielectric layer, then forming openings in the low k layer in portions of the low k layer needing reinforcement, and then filling the openi... | 05/20/2003 |
| 6566171 | Fuse construction for integrated circuit structure having low dielectric constant dielectric material Fuses, and optionally metal pads, are formed over a layer of low k dielectric material structure having first openings lined with conductive barrier material and filled to form metal interconnects in the upper surface of the low k dielectric material. A d... | 05/20/2003 |
| 6562735 | Control of reaction rate in formation of low k carbon-containing silicon oxide dielectric material using organosilane, unsubstituted silane, and hydrogen peroxide reactants Control of a reaction between a peroxide oxidizing agent and a carbon-substituted silane to form a low k carbon-containing silicon oxide dielectric material is achieved, in a first embodiment, by adding, to the carbon-substituted silane reactant, silane (... | 05/13/2003 |
| 6562700 | Process for removal of resist mask over low k carbon-doped silicon oxide dielectric material of an integrated circuit structure, and removal of residues from via etch and resist mask removal A process is disclosed for removing a photoresist mask used to form openings in an underlying layer of low k carbon-doped silicon oxide dielectric material of an integrated circuit structure formed on a semiconductor substrate, which comprises exposing th... | 05/13/2003 |
| 6559048 | Method of making a sloped sidewall via for integrated circuit structure to suppress via poisoning Via poisoning of vias formed in low k carbon-containing silicon oxide dielectric material is suppressed by forming the via in a layer of such dielectric material with a smooth inwardly sloped sidewall. Such a sloped sidewall via can be etched in a low k d... | 05/06/2003 |
| 6559033 | Processing for forming integrated circuit structure with low dielectric constant material between closely spaced apart metal lines Protective caps are formed over horizontally closely spaced apart metal lines of an integrated circuit structure. Low k silicon oxide dielectric material is then deposited over and between the metal lines and over protective caps on the lines. After the f... | 05/06/2003 |
| 6537923 | Process for forming integrated circuit structure with low dielectric constant material between closely spaced apart metal lines A capping layer of an insulator such as silicon nitride is formed over horizontally closely spaced apart metal lines on an oxide layer of an integrated circuit structure formed on a semiconductor substrate. Low k silicon oxide dielectric material which ex... | 03/25/2003 |
| 6537896 | Process for treating porous low k dielectric material in damascene structure to form a non-porous dielectric diffusion barrier on etched via and trench surfaces in the porous low k dielectric material A process for forming a non-porous dielectric diffusion barrier layer on etched via and trench sidewall surfaces in a layer of porous low k dielectric material comprises exposing such etched surfaces to a plasma formed from one or more gases such as, for ... | 03/25/2003 |
| 6528423 | PROCESS FOR FORMING COMPOSITE OF BARRIER LAYERS OF DIELECTRIC MATERIAL TO INHIBIT MIGRATION OF COPPER FROM COPPER METAL INTERCONNECT OF INTEGRATED CIRCUIT STRUCTURE INTO ADJACENT LAYER OF LOW K DIELECTRIC MATERIAL A process for forming an integrated circuit structure characterized by formation of an improved barrier layer for protection against migration of copper from a copper-containing layer into low k dielectric material while mitigating undesired increase in d... | 03/04/2003 |
| 6524974 | FORMATION OF IMPROVED LOW DIELECTRIC CONSTANT CARBON-CONTAINING SILICON OXIDE DIELECTRIC MATERIAL BY REACTION OF CARBON-CONTAINING SILANE WITH OXIDIZING AGENT IN THE PRESENCE OF ONE OR MORE REACTION RETARDANTS An improvement in the formation of low dielectric constant carbon-containing silicon oxide dielectric material by reacting a carbon-substituted silane with an oxidizing agent is described, wherein the process is carried out in the presence of a reaction r... | 02/25/2003 |
| 6511925 | Process for forming high dielectric constant gate dielectric for integrated circuit structure In accordance with the invention a high-k gate dielectric is formed by the steps of first forming a silicon oxide layer over a silicon substrate and then exposing the silicon oxide to a flux of low energy plasma containing metal ions which, when inserted ... | 01/28/2003 |
| 6506678 | Integrated circuit structures having low k porous aluminum oxide dielectric material separating aluminum lines, and method of making same An aluminum layer formed over an integrated circuit structure is patterned to form a plurality of aluminum metal lines. The patterned aluminum metal lines are then anodized in an acid anodizing bath to form anodized aluminum oxide on the exposed sidewall ... | 01/14/2003 |
