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| Number | Title | Issue Date |
| 6408300 | Multidimensional indexing structure for use with linear optimization queries Linear optimization queries, which usually arise in various decision support and resource planning applications, are queries that retrieve top N data records (where N is an integer greater than zero) which satisfy a specific optimization criterion. The op... | 06/18/2002 |
| 6389505 | Restore tracking system for DRAM A system and method for reducing the number of refresh actions needed to maintain data in a DRAM, by restoring only those cells which haven't been read from or written to within an allotted data retention time. One embodiment describes a restore tracking ... | 05/14/2002 |
| 6289085 | Voice mail system, voice synthesizing device and method therefor The reception part 30 outputs the text and the header of the received electronic mail to the voice synthesizing part 32. The voice font switching part 326 outputs the sander ID contained in the header to the voice font searching part 328. The voice font s... | 09/11/2001 |
| 6275612 | Character data input apparatus and method thereof When a user points a hot spot 322-i, a selection frame 38 is displayed in correlation to input frames 320-i (hot spot 322-i). The selection frame 38 includes within a same window a list of candidate characters of a handwritten character inputted to the in... | 08/14/2001 |
| 6246165 | Magnetic channel cathode An electron source comprises a permanent magnet having channels within the plate extending between opposite poles of the magnet. The internal surfaces of the channels are conductive. A cathode means is located at a first pole of the magnet, at one end of ... | 06/12/2001 |
| 6240216 | Method and apparatus for processing an image, storage medium for storing an image processing program A mask process such as smoothing of a graphic or a character drawn into a bit pattern is performed by using only SHIFT, logical NOT, AND, OR operations of bit strings, rather than using conditional branch instructions in the form of "IF THEN ELSE" and "SW... | 05/29/2001 |
| 6205427 | Voice output apparatus and a method thereof When a user depresses a normal mode key 180 of a key pad 18 the computer 16 provides a voice signal which reads text data aloud at a normal speed (for example, a speed at which an announcer reads aloud news in radio broadcasting). When the user depresses ... | 03/20/2001 |
| 6151266 | Asynchronous multiport register file with self resetting write operation Self-reset and write control circuits for high performance asynchronous multiport register files are disclosed. The high speed write operation is achieved by the combination of static data input and dynamic data control circuits. The write timing signal g... | 11/21/2000 |
| 5953701 | Speech recognition models combining gender-dependent and gender-independent phone states and using phonetic-context-dependence A method of gender dependent speech recognition includes the steps of identifying phone state models common to both genders, identifying gender specific phone state models, identifying a gender of a speaker and recognizing acoustic data from the speaker. ... | 09/14/1999 |
| 5930107 | Dual trench capacitor A dual trench structure for a high density trench DRAM. The dual trench structure, each of which can reside in part under the access device of a respective cell, does not require the use of expensive selective epi growth techniques. A sub-minimum lithogra... | 07/27/1999 |
| 5914695 | Omnidirectional dipole antenna The invention is a novel antenna configuration that has a substantially smaller size than existing antennas tuned to a given frequency. Compact size is provided without substantial loss in performance, making the antenna particularly suitable for hand-hel... | 06/22/1999 |
| 5899973 | Method and apparatus for adapting the language model's size in a speech recognition system In this speech recognition system, the size of the language model is reduced by discarding those n-grams that the acoustic part of the system can recognize most accurately without support from a language model. The n-grams can be discarded dynamically dur... | 05/04/1999 |
| 5890215 | Electronic computer memory system having multiple width, high speed communication buffer An electronic computer memory system has first and second intermediate memory levels for use between a central processing unit and a main memory level. One or more buffer arrays have two sets of bus lines. A first set of buffer array bus lines communicate... | 03/30/1999 |
| 5875426 | Recognizing speech having word liaisons by adding a phoneme to reference word models A method and system of recognizing speech. The method and system perform a fast match on a word in the string of speech to be recognized which generates a fast match list representing words in a system vocabulary that most likely match a current word to b... | 02/23/1999 |
| 5790696 | Image segmentation apparatus and a character recognition apparatus An apparatus for separating an image from a black frame quickly and precisely wherein corner coordinates for a character field are inferred by using a parameter relative to a character frame layout, and more precise corner coordinates are detected by pel ... | 08/04/1998 |
| 5787197 | Post-processing error correction scheme using a dictionary for on-line handwriting recognition A dictionary based post-processing technique for an on-line handwriting recognition system is described. An input word has all punctuation removed, and the word is checked against a word processing dictionary. If any word matches against the dictionary, i... | 07/28/1998 |
| 5760478 | Clock skew minimization system and method for integrated circuits A precise and highly controllable clock-distribution network is provided on one active substrate to distribute clock signals with minimal skew to another active substrate by connecting the substrates together face-to-face using flip-chip technology. Since... | 06/02/1998 |
| 5748012 | Methodology to test pulsed logic circuits in pseudo-static mode A pulsed logic circuit test methodology and circuitry therefor are disclosed. The methodology and circuitry allow the inhibiting of reset pulses, the ability to force resets and the ability to test the circuit in a pseudo-static mode of operation.... | 05/05/1998 |
| 5692281 | Method for making a dual trench capacitor structure A dual trench structure for a high density trench DRAM. The dual trench structure, each of which can reside in part under the access device of a respective cell, does not require the use of expensive selective epi growth techniques. A sub-minimum lithogra... | 12/02/1997 |
| 5684672 | Laptop computer with an integrated multi-mode antenna An antenna is integrated into the laptop to increase the efficiency, convenience and ruggedness of radio frequency transmission. The antenna extends from the laptop's cover when in use for maximum efficiency but retracts when not in use for ruggedness and... | 11/04/1997 |
| 5680509 | Method and apparatus for estimating phone class probabilities a-posteriori using a decision tree A method and apparatus for estimating the probability of phones, a-posteriori, in the context of not only the acoustic feature at that time, but also the acoustic features in the vicinity of the current time, and its use in cutting down the search-space i... | 10/21/1997 |
| 5675500 | Multi-chip device partitioning process An efficient method for partitioning, for example, FPGA devices is described which optimizes the number of devices required to implement a design. The method involves generating a hierarchical graph of a feasible bipartition of the cells of the design. Fe... | 10/07/1997 |
| 5675711 | Adaptive statistical regression and classification of data strings, with application to the generic detection of computer viruses A data string is a sequence of atomic units of data that represent information. In the context of computer data, examples of data strings include executable programs, data files, and boot records consisting of sequences of bytes, or text files consisting ... | 10/07/1997 |
| 5671330 | Speech synthesis using glottal closure instants determined from adaptively-thresholded wavelet transforms A speech synthesis system making use of a pitch-synchronous waveform overlap method to realize stable speech synthesis processing in which pitch shaking is negligible. The present invention is characterized in that glottal closure instants are used as ref... | 09/23/1997 |
| 5646058 | Method for fabricating a self-aligned double-gate MOSFET by selective lateral epitaxy A novel method of fabricating a double-gate MOSFET structure is disclosed. The method utilizes selective lateral epitaxial growth of silicon into a thin gap formed between two sacrificial dielectric films for accurate thickness control. The sacrificial fi... | 07/08/1997 |
| 5636364 | Method for enabling concurrent misses in a cache memory In a cache-to-memory interface, a means and method for timesharing a single bus to allow the concurrent processing of multiple misses. The multiplicity of misses can arise from a single processor if that processor has a nonblocking cache and/or does specu... | 06/03/1997 |
| 5634096 | Using virtual disks for disk system checkpointing A scheme is presented for storing data on disks in such a way that a checkpoint can easily be taken across several disks connected to different processors in a distributed or parallel computer. A checkpoint can be used to restore the entire disk system to... | 05/27/1997 |
| 5629858 | CMOS transistor network to gate level model extractor for simulation, verification and test generation A technique for extracting a gate level logic model from transistor networks has been described. The resultant logic model can be technology dependent or technology independent, depending on control parameters and environment of the program. It handles al... | 05/13/1997 |
| 5619665 | Method and apparatus for the transparent emulation of an existing instruction-set architecture by an arbitrary underlying instruction-set architecture The invention provides means and methods for extending an instruction-set architecture without impacting the software interface. This circumvents all software compatibility issues, and allows legacy software to benefit from new architectural extensions wi... | 04/08/1997 |
| 5613002 | Generic disinfection of programs infected with a computer virus A method for restoring a computer program infected with a computer virus to its non-viral condition. The method uses certain information about an uninfected host program recorded prior to infection without relying upon pre-existing knowledge of the comput... | 03/18/1997 |
| 5604368 | Self-aligned double-gate MOSFET by selective lateral epitaxy A novel method of fabricating a double-gate MOSFET structure is disclosed. The method utilizes selective lateral epitaxial growth of silicon into a thin gap formed between two sacrificial dielectric films for accurate thickness control. The sacrificial fi... | 02/18/1997 |
| 5593912 | SOI trench DRAM cell for 256 MB DRAM and beyond A trench SOI structure is described. The structure is useful, for instance in the fabrication of DRAM cells. The structure can be fabricated by extending the conventional substrate plate trench cell. The SOI cell eliminates the parasitic trench sidewall l... | 01/14/1997 |
| 5583059 | Fabrication of vertical SiGe base HBT with lateral collector contact on thin SOI A SiGe-HBT structure for device integration on thin-SOI substrates is disclosed. The emitter and base regions are vertical while the collector contact is lateral in the otherwise MOS-like device structure. This allows one to integrate a SiGe base, the dev... | 12/10/1996 |
| 5566342 | Scalable switch wiring technique for large arrays of processors Connections between the node switch sets associated with processors in large scalable processor arrays, such as those of the butterfly variety, are arranged, like the 2-D mesh array, in rows and columns between the node switch sets. Additional sets of swi... | 10/15/1996 |
| 5561383 | Switchable peak/average detect circuit A circuit that can switch between a peak detect and an averaging mode is described. In a preferred embodiment, when the circuit is in a peak detect mode a first transistor is on and a second is off, enabling an amplifier in the circuit to produce a signal... | 10/01/1996 |
| 5543731 | Dynamic and preset static multiplexer in front of latch circuit for use in static circuits A latch circuit. The circuit includes a static digital logic circuit, comprising a multiplexer having a plurality of static input data lines and one or more select lines for selecting data from one of the input lines as multiplexer output data; latching m... | 08/06/1996 |
| 5544162 | IP bridge for parallel machines This invention is a high performance, standard IO interconnect "bridge" hardware for a parallel machine with a packet switching network in place. Combining new hardware and new software, this bridge connects parallel processors to the external world. The ... | 08/06/1996 |
| 5544260 | Silent training by error correction for on-line handwritting recognition systems A method for using information provided during error correction for modifying character prototypes in an on-line handwriting recognition system is disclosed. The method allows a user to correct misrecognized handwritten characters by overwriting directly ... | 08/06/1996 |
| 5529944 | Method of making cross point four square folded bitline trench DRAM cell The invention is a high density cross point folded bitline trench DRAM cell with a cell area of only 4 lithographic squares. The access device (transfer device) is vertically disposed on the side of a trench. In a preferred embodiment, poly spacer wordlin... | 06/25/1996 |
| 5522032 | Raid level 5 with free blocks parity cache A system for writing data to a disk array includes a cache memory coupled to the disk array for storing data indicative of locations on the disk array and parity blocks associated with parity groups including the locations. Each of the parity blocks inclu... | 05/28/1996 |
