Did You Know...
...that the video game, Pong, was invented by a guy who graduated at the bottom of his engineering class? Nolan Bushnell spent more time running the games at a local amusement park than he did on his studies at the University of Utah. His dreams of working for Disney's amusement empire were dashed when the company wouldn't hire him. Taking a boring job, Nolan daydreamed about electronic versions of popular games. He invented Pong, the first video game, and went on to found Atari Co.
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| Number | Title | Issue Date |
| 8185694 | Testing real page number bits in a cache directory Testing real page number bits in a cache directory is provided. A specification of a cache to be tested is retrieved in order to test the real page number bits of the cache directory associated with the cache. A range within a real page number address of the cache d... | 05/22/2012 |
| 8181050 | Adaptive throttling for data processing systems An adaptive throttling system for minimizing the impact of non-production work on production work in a computer system is provided. The adaptive throttling system throttles production work and non-production work to optimize production. The adaptive throttling syste... | 05/15/2012 |
| 8180941 | Mechanisms for priority control in resource allocation Mechanisms for priority control in resource allocation is provided. With these mechanisms, when a unit makes a request to a token manager, the unit identifies the priority of its request as well as the resource which it desires to access and the unit's resource acce... | 05/15/2012 |
| 8176339 | Method and system for managing peripheral connection wakeup in a processing system supporting multiple virtual machines A method and system for managing peripheral connection wakeup signaling in a processing system supporting multiple virtual machines provides a mechanism by which ownership of a peripheral having system wakeup capability is transferred between virtual machines. The p... | 05/08/2012 |
| 8176185 | Method of switching Internet personas based on URL A method of communicating with a remote site on a network by establishing different user personas respectively associated with different remote sites on the network, each user persona containing one or more attributes used in accessing the remote sites, and then acc... | 05/08/2012 |
| 8171476 | Wake-and-go mechanism with prioritization of threads A hardware private array is a thread state storage that is embedded within the processor or within logic associated with a bus or wake-and-go logic. The hardware private array and/or wake-and-go array may have a limited storage area. Therefore, each thread may have ... | 05/01/2012 |
| 8171464 | Efficient code generation using loop peeling for SIMD loop code with multile misaligned statements An approach is provided for vectorizing misaligned references in compiled code for SIMD architectures that support only aligned loads and stores. In this framework, a loop is first simdized as if the memory unit imposes no alignment constraints. The compiler then in... | 05/01/2012 |
| 8171448 | Structure for a livelock resolution circuit A design structure for a livelock resolution circuit is provided. When a bus unit detects a timeout condition, or potential timeout condition, the bus unit activates a livelock resolution request signal. A livelock resolution unit receives livelock resolution reques... | 05/01/2012 |
| 8171230 | PCI express address translation services invalidation synchronization with TCE invalidation A PCI Express (PCIe) computer system utilizes address translation services to translate virtual addresses from I/O device adaptors to physical addresses of system memory. A combined memory controller and host bridge uses a translation agent to convert the I/O addres... | 05/01/2012 |
| 8166246 | Chaining multiple smaller store queue entries for more efficient store queue usage A computer implemented method, a processor chip, a data processing system, and computer program product in a data processing system process information in a store cache of a data processing system. The store cache receives a first entry that includes a first address... | 04/24/2012 |
| 8166085 | Reducing the latency of sum-addressed shifters The present invention provides for calculating a shift amount as a function of a plurality of numbers. At least one decoder and the at least one adder are coupled in parallel. A shifter is configured to compute a value in a plurality of shift stages, and wherein a b... | 04/24/2012 |
| 8153516 | Method of ball grid array package construction with raised solder ball pads The present invention provides for a BGA solder ball interconnection to an outer conductive layer of a laminated circuit assembly having an underlying circuit layer. The invention includes a raised BGA solder ball pad substantially co-planar with the outer conductiv... | 04/10/2012 |
| 8150672 | Structure for improved logic simulation using a negative unknown boolean state A system and method for simulating a circuit design using both an unknown Boolean state and a negative unknown Boolean state is provided. When the circuit is simulated, one or more initial simulated logic elements are initialized to the unknown Boolean state. The in... | 04/03/2012 |
| 8146067 | Efficient data reorganization to satisfy data alignment constraints Vectorizing misaligned references in compiled code for SIMD architectures that support only aligned loads and stores is presented. In the framework presented herein, a loop is first simdized as if the memory unit imposes no alignment constraints. The compiler then i... | 03/27/2012 |
| 8146064 | Dynamically controlling a prefetching range of a software controlled cache Dynamically controlling a prefetching range of a software controlled cache is provided. A compiler analyzes source code to identify at least one of a plurality of loops that contain irregular memory references. For each irregular memory reference in the source code,... | 03/27/2012 |
| 8145849 | Wake-and-go mechanism with system bus response A wake-and-go mechanism is provided for a data processing system. The wake-and-go mechanism is configured to issue a look-ahead load command on a system bus to read a data value from a target address and perform a comparison operation to determine whether the data v... | 03/27/2012 |
| 8145819 | Method and system for stealing interrupt vectors A system for stealing interrupt vectors from an operating system. Custom interrupt handler extensions are copied into an allocated block of memory from a kernel module. Also, operating system interrupt handlers are copied into a reserved space in the allocated block... | 03/27/2012 |
| 8144689 | Controlling asynchronous clock domains to perform synchronous operations A mechanism for controlling asynchronous clock domains to perform synchronous operations is provided. With the mechanism, when a synchronous operation is to be performed on a chip, the latches of the functional elements of the chip are controlled by a synchronous cl... | 03/27/2012 |
| 8144582 | Differentiating blade destination and traffic types in a multi-root PCIe environment Mechanisms for differentiating traffic types per host system blade in a multi-root PCI Express environment are provided. The mechanisms generate a first mapping data structure that, for each single-root virtual hierarchy in the multi-root data processing system, ass... | 03/27/2012 |
| 8141094 | Distribution of resources for I/O virtualized (IOV) adapters and management of the adapters through an IOV management partition via user selection of compatible virtual functions Mechanisms to address the situation where an input/output (I/O) fabric is shared by more than one logical partition (LPAR) and where each LPAR can share with the other LPARs an I/O adapter (LOA) are provided. In particular, each LPAR is assigned its own separate add... | 03/20/2012 |
| 8141093 | Management of an IOV adapter through a virtual intermediary in an IOV management partition Mechanisms that address the situation where an input/output (I/O) fabric is shared by more than one logical partition (LPAR) and where each LPAR can share with the other LPARs an I/O adapter (IOA) are provided. In particular, each LPAR is assigned its own separate a... | 03/20/2012 |
| 8141092 | Management of an IOV adapter through a virtual intermediary in a hypervisor with functional management in an IOV management partition Mechanisms are provided for an I/O virtualization management partition (IMP) to control the shared functionality of an I/O virtualization (IOV) enabled I/O adapter (IDA) through a physical function (PF) of the IOA while the virtual functions (VFs) are assigned to cl... | 03/20/2012 |
| 8141067 | Ensuring maximum code motion of accesses to DMA buffers A “kill” intrinsic that may be used in programs for designating specific data objects as having been “killed” by a preceding action is provided. The concept of a data object being “killed” is that the compiler is informed that no operations (e.g., loads ... | 03/20/2012 |
| 8140824 | Secure code authentication A computer program product comprises a computer useable medium having a computer readable program for authentication of code, such as boot code. A memory addressing engine is employable to select a portion of a memory, as a function of a step value, as a first input... | 03/20/2012 |
| 8140317 | Device simulation method and system A simulation method and system. The method includes receiving by a simulation engine in a device driver, input simulation parameters data associated with a simulation process. The simulation engine calculates a simulated scaled down process time period for a device ... | 03/20/2012 |
| 8135746 | Management of symbolic links Disclosed is a method of creating a symbolic link in a source file system to a target file in a target file system, the method including querying the target file system for an identifier of the target file; incrementing a reference counter of the target file, the re... | 03/13/2012 |
| 8132169 | System and method for dynamically partitioning an application across multiple processing elements in a heterogeneous processing environment A system and method for dividing an application into a number of logical program partitions is presented. Each of these logical program partitions are stored in a logical program package along with a execution monitor. The execution monitor runs in one of the proces... | 03/06/2012 |
| 8131974 | Access speculation predictor implemented via idle command processing resources An access speculation predictor is provided that may be implemented using idle command processing resources, such as registers of idle finite state machines (FSMs) in a memory controller. The access speculation predictor may predict whether to perform speculative re... | 03/06/2012 |
| 8131906 | Voltage indicator signal generation system and method The present invention provides for a system comprising a peripheral component interface (PCI) host bridge. The PCI host bridge is configured to be coupled to a PCI bus, and to receive a system reset signal, to generate a PCI bus reset signal based on the received sy... | 03/06/2012 |
| 8131795 | High speed adder design for a multiply-add based floating point unit A method is provided for improving a high-speed adder for Floating-Point Units (FPU) in a given computer system. The improved adder utilizes a compound incrementer, a compound adder, a carry network, an adder control/selector, and series of multiplexers (muxes). The... | 03/06/2012 |
| 8128498 | Configure offline player behavior within a persistent world game A mechanism is provided for configuring offline player behavior within a persistent world game. A player agent for an offline player includes an event monitor that monitors for events that occur in a persistent virtual world maintained by a game server. When a game ... | 03/06/2012 |
| 8127192 | Predicting lwarx and stwcx instructions in test pattern generation and simulation for processor design verification/validation in interrupt mode During a test pattern build, a test pattern generator pseudo-randomly selects an address for a selected lwarx instruction and builds the lwarx instruction using the pseudo-random address into a test pattern. Subsequently, the test pattern generator builds a store in... | 02/28/2012 |
| 8127106 | Access speculation predictor with predictions based on a domain indicator of a cache line An access speculation predictor may predict whether to perform speculative retrieval of data for a data request from a main memory based on whether or not a domain indicator in the data request indicates that the cache line corresponding to the data has a special in... | 02/28/2012 |
| 8127080 | Wake-and-go mechanism with system address bus transaction master A wake-and-go mechanism is provided for a data processing system. The wake-and-go mechanism is configured to issue a look-ahead load command on a system bus to read a data value from a target address and perform a comparison operation to determine whether the data v... | 02/28/2012 |
| 8122223 | Access speculation predictor with predictions based on memory region prior requestor tag information An access speculation predictor may predict whether to perform speculative retrieval of data for a data request from a main memory based on whether or not a current requestor tag matches a previous requestor tag. In particular, a first address and a first requester ... | 02/21/2012 |
| 8108846 | Compiling scalar code for a single instruction multiple data (SIMD) execution engine A mechanism is provided for performing scalar operations using a SIMD data parallel execution unit. With the mechanisms of the illustrative embodiments, scalar operations in application code are identified that may be executed using vector operations in a SIMD data ... | 01/31/2012 |
| 8108842 | Method and apparatus for performing native binding A native binding technique is provided for inserting calls to native functions during translation of subject code to target code, such that function calls in the subject program to subject code functions are replaced in target code with calls to native equivalents o... | 01/31/2012 |
| 8108813 | Structure for a circuit obtaining desired phase locked loop duty cycle without pre-scaler A design structure for a circuit for obtaining a desired phase locked loop (PLL) duty cycle without a pre-scaler is provided. The PLL circuit of the illustrative embodiments utilizes two separate loops that simultaneously operate on the VCO. One loop ensures the fre... | 01/31/2012 |
| 8108657 | Handling floating point operations A computing system capable of handling floating point operations during program code conversion is described, comprising a processor including a floating point unit and an integer unit. The computing system further comprises a translator unit arranged to receive sub... | 01/31/2012 |
| 8108564 | System and method for a configurable interface controller A flexible input/output controller logic interfaces with existing input/output controllers (IOC's) in order to configure the amount of data sent to and received from the IOC's. The flexible I/O interface receives data from a component at a rate determined by the par... | 01/31/2012 |
