Did You Know...
...that Thomas Edison's patent application on his phonograph was approved by the Patent Office in just seven weeks? In contrast, it took Gordon Gould, the inventor of the laser, 30 years to obtain his patent -- finally awarded in 1988!
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| Number | Title | Issue Date |
| 8185371 | Modeling full and half cycle clock variability A modeling system includes a processor with software that performs static timing analysis (STA) on a design model. STA software executes a static timing analysis (STA) run with shortened clock cycles to model full cycle clock variability. Designers or other entities... | 05/22/2012 |
| 8108618 | Method and apparatus for maintaining memory data integrity in an information handling system using cache coherency protocols An information handling system includes a processor integrated circuit including multiple processors with respective processor cache memories. Enhanced cache coherency protocols achieve cache memory integrity in a multi-processor environment. A processor bus control... | 01/31/2012 |
| 8103852 | Information handling system including a processor with a bifurcated issue queue An information handling system includes a processor with a bifurcated unified issue queue that may perform unified issue queue VSU store instruction dependency operations. The bifurcated unified issue queue BUIQ maintains VSU store instructions in the form of intern... | 01/24/2012 |
| 8073669 | Method and apparatus for detecting clock gating opportunities in a pipelined electronic circuit design A pipeline electronic circuit and design methodology enables power conservation in the stages of the pipeline via a simulation that identifies clock-gating opportunities among the stages of the pipeline. In one embodiment, simulation results assist a designer in the... | 12/06/2011 |
| 8073668 | Method and apparatus for testing a full system integrated circuit design by statistical fault injection using hardware-based simulation A test system tests a full system integrated circuit (IC) model that includes a device under test (DUT) IC model and a support IC model. A test manager information handling system (IHS) maps the full system IC model on a hardware accelerator simulator via an interfa... | 12/06/2011 |
| 8055761 | Method and apparatus for providing transparent network connectivity A client information handling system (IHS) connects to a network in a manner that provides transparent network connectivity. In one embodiment, the client IHS includes a polling application that monitors the network connection to determine if the client IHS exhibits... | 11/08/2011 |
| 8010656 | Method and apparatus for dynamically granting or denying access to an electronic calendar A calendar system includes a calendar requester client and a calendar owner client that couple to a calendar server via one or more networks therebetween. In one embodiment, when the calendar server denies a particular calendar requester access to the calendar owner... | 08/30/2011 |
| 8010334 | Method and apparatus for evaluating integrated circuit design performance using basic block vectors, cycles per instruction (CPI) information and microarchitecture dependent information A test system or simulator includes an integrated circuit (IC) benchmark software program that executes workload program software on a semiconductor die IC design model. The benchmark software program includes trace, simulation point, basic block vector (BBV) genera... | 08/30/2011 |
| 8006070 | Method and apparatus for inhibiting fetch throttling when a processor encounters a low confidence branch instruction in an information handling system An information handling system includes a processor that throttles an instruction fetcher whenever a group of instructions in a branch instruction queue together exhibits a confidence in the accuracy of branch predictions of branch instructions therein that is less ... | 08/23/2011 |
| 7962911 | Method and apparatus for preventing undesired termination of a process in an information handling system An information handling system (IHS) employs operating system software to manage IHS resources. The operating system software manages software application programs as processes executing within the IHS. The processes run in foreground and background mode within the ... | 06/14/2011 |
| 7925853 | Method and apparatus for controlling memory array gating when a processor executes a low confidence branch instruction in an information handling system An information handling system includes a processor with an array power management controller. The array power management controller gates off a memory array, such as a cache, to conserve power whenever a group of instructions in a branch instruction queue together ... | 04/12/2011 |
| 7917730 | Processor chip with multiple computing elements and external i/o interfaces connected to perpendicular interconnection trunks communicating coherency signals via intersection bus controller A multi-chip processor apparatus includes multiple processor chips on a substrate. At least one of the multiple processor chips includes a die with a primary interconnect trunk that communicates information between multiple compute elements situated along the primar... | 03/29/2011 |
| 7904870 | Method and apparatus for integrated circuit design model performance evaluation using basic block vector clustering and fly-by vector clustering A test system or simulator includes an enhanced IC test application sampling software program that executes test application software on a semiconductor die IC design model. The enhanced test application sampling software may include trace, simulation point, CPI err... | 03/08/2011 |
| 7849241 | Memory compression method and apparatus for heterogeneous processor architectures in an information handling system The disclosed heterogeneous processor compresses information to more efficiently store the information in a system memory coupled to the processor. The heterogeneous processor includes a general purpose processor core coupled to one or more processor cores that exhi... | 12/07/2010 |
| 7865650 | Processor with coherent bus controller at perpendicularly intersecting axial bus layout for communication among SMP compute elements and off-chip I/O elements A symmetric multi-processing (SMP) processor includes a primary interconnect trunk for communication of information between multiple compute elements situated along the primary interconnect trunk. The processor also includes a secondary interconnected trunk that may... | 01/04/2011 |
| 7863958 | High speed clock signal duty cycle adjustment A clock signal duty cycle adjustment circuit includes a duty cycle correction circuit that receives a clock input signal that may need duty cycle correction. The duty cycle correction circuit may derive first and second differential clock signals from the clock inpu... | 01/04/2011 |
| 7863106 | Silicon interposer testing for three dimensional chip stack A testing method for a silicon interposer employs a test probe and an electrically conductive glass handler. The silicon interposer includes multiple interconnects that extend between the opposed major surfaces of the interposer, namely from a test side of the inter... | 01/04/2011 |
| 7844928 | Method and apparatus for evaluating integrated circuit design performance using enhanced basic block vectors that include data dependent information A test system or simulator includes an IC benchmark software program that executes application software on a semiconductor die IC design model. The benchmark software includes trace, simulation point, clustering and other programs. IC designers utilize the benchmark... | 11/30/2010 |
| 7831812 | Method and apparatus for operating an age queue for memory request operations in a processor of an information handling system A processor includes a processor core with a core interface unit that includes an age queue and a request queue. The core interface unit receives load requests from the processor core. The request queue stores the requests in respective slots of the request queue. T... | 11/09/2010 |
| 7818619 | Method and apparatus for debugging application software in information handling systems over a memory mapping I/O bus A test system includes a debugging system and a system under test (SUT). The debugging system includes a debugging processor that couples to an SUT processor in the SUT via a memory mapping interface bus therebetween. In one embodiment, the debugging processor opera... | 10/19/2010 |
| 7793125 | Method and apparatus for power throttling a processor in an information handling system A power system couples to a multi-core processor to provide power to the processor. The power system throttles at least one of the cores of the processor when the power that the processor consumes from the power system exceeds a predetermined threshold power. The po... | 09/07/2010 |
| 7791509 | Preprocessing variable-length code (VLC) bitstream information An information handling system includes a processor that may perform preprocessing on a variable-length code (VLC) bitstream before decoding the bitstream. The bitstream includes multiple codewords. The processor analyzes incoming VLC bitstream information and gener... | 09/07/2010 |
| 7777653 | Decoding variable-length code (VLC) bitstream information An information handling system includes a processor that may perform decoding of a variable-length code (VLC) bitstream after preprocessing the bitstream. The bitstream includes multiple VLC symbols as binary codewords. The processor analyzes incoming VLC bitstream ... | 08/17/2010 |
| 7737763 | Virtual electronic fuse apparatus and methodology A virtual electronic fuse apparatus and methodology are disclosed that permit the state of an electronic fuse to change from an un-blown state to a blown state and then back to a virtual un-blown state. In one embodiment, the electronic fuse may change from the virt... | 06/15/2010 |
| 7650555 | Method and apparatus for characterizing components of a device under test using on-chip trace logic analyzer A test system is disclosed wherein a device under test (DUT) includes a trace logic analyzer (TLA) that receives and stores test data. The test system includes both a master tester and a slave tester. The slave tester operates at a high speed data rate substantially... | 01/19/2010 |
| 7646177 | Design structure for a duty cycle measurement apparatus that operates in a calibration mode and a test mode A design structure for an on-chip duty cycle measurement system may be embodied in a machine readable medium for designing, manufacturing or testing an integrated circuit. The design structure may embody an apparatus that measures the duty cycle of a reference clock... | 01/12/2010 |
| 7620126 | Method and apparatus for detecting frequency lock in a system including a frequency synthesizer A frequency synthesizer lock detection system is disclosed that distributes a frequency synthesizer output signal across a distribution network to one or more receptor circuits. The distribution network may exhibit delay and other distortion that may cause the downs... | 11/17/2009 |
| 7617403 | Method and apparatus for controlling heat generation in a multi-core processor The disclosed methodology and apparatus may reduce heat generation in a multi-core processor. In one embodiment, a multi-core processor cycles selected processor cores off in a predetermined pattern across the processor die over time to reduce the average heat gener... | 11/10/2009 |
| 7617059 | Method and apparatus for measuring the duty cycle of a digital signal The disclosed methodology and apparatus measures the duty cycle of a clock signal. A variable duty cycle circuit receives a clock signal from a clock signal generator. The variable duty cycle circuit adjusts the duty cycle of the clock signal by an amount dependent ... | 11/10/2009 |
| 7595675 | Duty cycle measurement method and apparatus that operates in a calibration mode and a test mode The disclosed methodology and apparatus measure the duty cycle of a reference clock signal that a clock circuit supplies to a duty cycle measurement (DCM) circuit. In one embodiment, the DCM circuit includes a capacitor driven by a charge pump. The reference clock s... | 09/29/2009 |
| 7590194 | Information handling system capable of detecting frequency lock of signals downstream from a signal synthesized by frequency synthesizer An information handling system including a frequency synthesizer lock detection system is disclosed that distributes a frequency synthesizer output signal across a distribution network to one or more receptor circuits. The distribution network may exhibit delay and ... | 09/15/2009 |
| 7584369 | Method and apparatus for monitoring and controlling heat generation in a multi-core processor The disclosed methodology and apparatus may control heat generation in a multi-core processor. In one embodiment, each processor core includes a temperature sensor that reports temperature information to a processor controller. If a particular processor core exceeds... | 09/01/2009 |
| 7574642 | Multiple uses for BIST test latches A method is provided to utilize built-in self test (BIST) latches for multiple purposes. Conventionally, BIST latches are single purpose. Hence, separate latches are utilized for array built-in self test (ABIST) and logic built-in self test (LBIST) operations. By ha... | 08/11/2009 |
| 7506071 | Methods for managing an interactive streaming image system Methods for managing an interactive streaming image system are disclosed. More particularly, hardware and/or software for generating, encoding, and transmitting image frames to an interactive client are disclosed. One embodiment provides a method for streaming image... | 03/17/2009 |
| 7503025 | Method to generate circuit energy models for macros containing internal clock gating A method, a computer program, and an apparatus are provided for generating circuit energy models for a macro containing internal clock gating. Circuit energy models are used to estimate system power consumption. The present invention enables circuit energy models to... | 03/10/2009 |
| 7496776 | Power throttling method and apparatus Disclosed is an apparatus which deactivates both the AC as well as the DC component of power for various functions in a CPU. The CPU partitions dataflow registers and arithmetic units such that voltage can be removed from the upper portion of dataflow registers when... | 02/24/2009 |
| 7496570 | Interactive filtering model to enhance a software component meta management system Provided is a method for generating an on-demand, custom runtime solution to a user or business's computing needs. A library of software components corresponding to different computing tasks of a business situation is created. Each software component is associated w... | 02/24/2009 |
| 7475247 | Method for using a portable computing device as a smart key device A first data processing system, which includes a first cryptographic device, is communicatively coupled with a second data processing system, which includes a second cryptographic device. The cryptographic devices then mutually authenticate themselves. The first cry... | 01/06/2009 |
| 7475086 | Method of automatically removing leading and trailing space characters from data being entered into a database system A computer Implemented method of automatically removing space characters from data being entered into a database system are provided. When a user creates a table in a database system into which data having leading and/or trailing character spaces may be entered, the... | 01/06/2009 |
| 7469357 | Method and apparatus for dynamic power management in an execution unit using pipeline wave flow control Power is conserved by dynamically applying clocks to execution units in a pipeline of a microprocessor. A clock to an execution unit is applied only when an instruction to the execution unit is valid. At other times when the execution unit needs not to be operationa... | 12/23/2008 |
