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...that the first rickshaw was invented in 1869 by an American Baptist minister, the Rev. E. Jonathan Scobie, to transport his invalid wife around the streets of Yokohama?
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| Number | Title | Issue Date |
| 8175532 | Apparatus and method for wireless communication via at least one of directional and omni-direction antennas Techniques for using at least one of omni-directional and directional antennas for communication are described. A station may be equipped antenna elements selectable for use as an omni-directional antenna or one or more directional antennas. The station may select t... | 05/08/2012 |
| 8169977 | Methods and apparatus for characterizing noise in a wireless communications system Improved pilot signal sequences which facilitate multiple channel quality measurements, e.g., through the use of different signal pilot transmission power levels, are described. In various implementations the transmitted pilot sequences facilitate determining the co... | 05/01/2012 |
| 8161446 | System and method of connecting a macro cell to a system power supply A system and method of connecting a macro cell to a system power supply network is disclosed. In a particular embodiment, the method includes determining a distance of an edge of the macro cell from a power line or a ground line of the system power supply network. T... | 04/17/2012 |
| 8161430 | System and method of resistance based memory circuit parameter adjustment Systems and methods of resistance based memory circuit parameter adjustment are disclosed. In a particular embodiment, a method of determining a set of parameters of a resistance based memory circuit includes selecting a first parameter based on a first predetermine... | 04/17/2012 |
| 8159870 | Array structural design of magnetoresistive random access memory (MRAM) bit cells Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) bit cells are disclosed. The bit cells include a source line formed in a first plane and a bit line formed in a second plane. The bit line has a longitudinal axis that is parallel to a longitudina... | 04/17/2012 |
| 8159009 | Semiconductor device having strain material A semiconductor device having strain material is disclosed. In a particular embodiment, the semiconductor device includes a first cell including a first gate between a first drain and a first source. The semiconductor device also includes a second cell adjacent to t... | 04/17/2012 |
| 8154903 | Split path sensing circuit A sensing circuit is disclosed. The sensing circuit includes a first path including a first resistive memory device and a second path including a reference resistive memory device. The first path is coupled to a first split path including a first load transistor and... | 04/10/2012 |
| 8143749 | Dual current switch detection circuit with selective activation A dual current switch detection circuit with selective activation is disclosed. In a particular embodiment, the switch detection circuit comprises an input node coupled to a switch to receive an input signal from the switch, a first current source coupled to the inp... | 03/27/2012 |
| 8139426 | Dual power scheme in memory circuit A semiconductor memory device includes address signal level shifters configured to transform a low level address signal into a higher level address signal. A decoder is configured to receive the higher level address signal and, in response, provide word line signals... | 03/20/2012 |
| 8138814 | High signal level compliant input/output circuits A signal driver for an interface circuit has a first stage level shifter to accept input signals and output signals at a first signal level. The signal driver also has a second stage level shifter coupled to the first stage level shifter to output signals at a secon... | 03/20/2012 |
| 8134931 | Apparatus and method of generating and maintaining orthogonal connection identifications (CIDs) for wireless networks A first device is configured to select and utilize a connection identifier (CID) for a peer-to-peer communication connection between the first device and a second device in a wireless communications network. The CID is selected from a predetermined set of a pluralit... | 03/13/2012 |
| 8130958 | Transmit power control for wireless security The present invention provides a method for establishing a secure channel between wireless devices. The method involves reducing the transmit power of the devices in conjunction with placing the devices in close proximity to one another. By reducing the transmit pow... | 03/06/2012 |
| 8130534 | System and method to read and write data a magnetic tunnel junction element A system and method to read and write data in magnetic random access memories are disclosed. In a particular embodiment, a device includes a spin transfer torque magnetic tunnel junction (STT-MTJ) element and a transistor with a first gate and a second gate coupled ... | 03/06/2012 |
| 8125040 | Two mask MTJ integration for STT MRAM A method for forming a magnetic tunnel junction (MTJ) for magnetic random access memory (MRAM) using two masks includes depositing over an interlevel dielectric layer containing an exposed first interconnect metallization, a first electrode, a fixed magnetization la... | 02/28/2012 |
| 8120989 | Concurrent multiple-dimension word-addressable memory architecture An N-dimension addressable memory. The memory includes an N-dimension array of bit cells and logic configured to address each bit cell using N-Dimension Addressing (NDA), where N is at least two and the array of bit cells is addressable by N orthogonal address space... | 02/21/2012 |
| 8120126 | Magnetic tunnel junction device and fabrication A magnetic tunneling junction device and fabrication method is disclosed. In a particular embodiment, the method includes depositing a capping material on a free layer of a magnetic tunneling junction structure to form the capping layer and oxidizing a portion of th... | 02/21/2012 |
| 8111088 | Level shifter with balanced duty cycle A level shifter and method are provided for balancing a duty cycle of a signal. An input circuit receives a differential logic signal with two complimentary logic levels. A level transition balancing circuit balances the rise and fall times of a level shifted versio... | 02/07/2012 |
| 8107280 | Word line voltage control in STT-MRAM Systems, circuits and methods for controlling the word line voltage applied to word line transistors in Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) are disclosed. One embodiment is directed to a STT-MRAM including a bit cell having a magnet... | 01/31/2012 |
| 8106699 | High signal level compliant input/output circuits A level shifter has at least one of either a pull up or a pull down circuit. The circuit is made of electronic components with reliability limits less than a maximum signal level output by the level shifter. The level shifter also has a timing circuit coupled to at ... | 01/31/2012 |
| 8103994 | Generating cutting forms along current flow direction in a circuit layout Metal is deleted from portions of metal wires in an integrated circuit layout, based upon a width of the metal wires. Preliminary cutting forms having a length and a width are inserted with a first orientation in the portions of metal wire. It is determined if the w... | 01/24/2012 |
| 8102720 | System and method of pulse generation In a particular embodiment, a device includes a reference voltage circuit to generate a controlled voltage. The device includes a frequency circuit configured to generate a frequency output signal having a pre-set frequency and a counter to generate a count signal b... | 01/24/2012 |
| 8094486 | Pad design with buffers for STT-MRAM or other short pulse signal transmission A Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) bit cell array is provided. The STT-MRAM array includes a STT-MRAM bit cell and an input net coupled to the STT-MRAM bit cell. The STT-MRAM array includes a pulse signal input pad and a buffer c... | 01/10/2012 |
| 8086985 | Automatic alignment of macro cells In a particular embodiment, a method is disclosed that includes detecting a first pitch between at least two lines (e.g. a power line and a ground line) of a first reference macro. The method also includes generating a virtual grid based on the first pitch and align... | 12/27/2011 |
| 8085581 | STT-MRAM bit cell having a rectangular bottom electrode plate and improved bottom electrode plate width and interconnect metal widths A Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) bit cell is provided. The STT-MRAM includes a rectangular bottom electrode (BE) plate, and a storage element on the rectangular bottom electrode (BE) plate. A difference between a width of the r... | 12/27/2011 |
| 8082401 | Self-timing for a multi-ported memory system Multi-ported memory systems (e.g., register files) employ self-timing for operational synchronization. Thus, rather than using a reference clock duty cycle for operational synchronization, as in conventional multi-ported register files, embodiments of the present di... | 12/20/2011 |
| 8081037 | Ring oscillator using analog parallelism An apparatus including a ring oscillator and related methods are disclosed. The ring oscillator includes at least two ring loops. A first ring loop includes a plurality of series coupled delay cells. At least one additional ring loop includes a plurality of series c... | 12/20/2011 |
| 8080862 | Systems and methods for enabling ESD protection on 3-D stacked devices An electrostatic discharge (ESD) protection device is fabricated in a vertical space between active layers of stacked semiconductor dies thereby utilizing space that would otherwise be used only for communication purposes. The vertical surface area of the through si... | 12/20/2011 |
| 8077504 | Shallow trench type quadri-cell of phase-change random access memory (PRAM) A method of forming a phase-change random access memory (PRAM) cell and PRAM arrangement, and embodiments of phase-change random access memory (PRAM) cells and PRAM arrangements are disclosed. A phase-change random access memory (PRAM) cell includes a bottom electro... | 12/13/2011 |
| 8076768 | IC interconnect A multi-tiered IC device contains a first die including a substrate with a first and second set of vias. The first set of vias extends from one side of the substrate, and the second set of vias extend from an opposite side of the substrate. Both sets of vias are cou... | 12/13/2011 |
| 8067816 | Techniques for placement of active and passive devices within a chip A semiconductor die includes a semiconductive substrate layer with first and second sides, a metal layer adjacent the second side of the semiconductive substrate layer, one or more active devices in an active layer on the first side of the semiconductive substrate l... | 11/29/2011 |
| 8063674 | Multiple supply-voltage power-up/down detectors A multiple supply voltage device includes an input/output (I/O) network operative at a first supply voltage, a core network coupled to the I/O network and operative at a second supply voltage, and a power-on-control (POC) network coupled to the I/O network and the c... | 11/22/2011 |
| 8037385 | Scan chain circuit and method A scan chain circuit is disclosed. The scan chain circuit includes a chain of serially coupled clocked circuits. In a first mode of operation, each of the clocked circuits toggles in response to a rising edge of a clock signal. In a second mode of operation, a first... | 10/11/2011 |
| 8030982 | Systems and methods using improved clock gating cells A clock gating cell that comprises a latch in communication with an input enable logic and an output logic circuit, wherein the latch includes a pull-up and/or a pull-down circuit at an input node of the output logic circuit and circuitry preventing premature charge... | 10/04/2011 |
| 7979832 | Process variation tolerant memory design Methods and systems for designing process variation tolerant memory are disclosed. A memory circuit is divided into functional blocks. A statistical distribution is calculated for each of the functional blocks. Then, the distributions of each block are combined to v... | 07/12/2011 |
| 7979684 | Method and context switch device for implementing design-for-testability functionality of latch-based register files A method of changing execution contexts is provided that includes receiving a context selection input. In a first clock phase, the method includes shifting data from a first latch element of a normal execution context to a second latch element of the normal executio... | 07/12/2011 |
| 7962681 | System and method of conditional control of latch circuit devices A circuit device includes a first input to receive a reset control signal and a second input coupled to an output of a latch. The circuit device also includes a logic circuit adapted to conditionally reset the latch based on a state of the output in response to rece... | 06/14/2011 |
| 7961502 | Non-volatile state retention latch Electronic circuits use latches including a magnetic tunnel junction (MTJ) structure and logic circuitry arranged to produce a selective state in the MTJ structure. Because the selective state is maintained magnetically, the state of the latch or electronic circuit ... | 06/14/2011 |
| 7941173 | Beacon signals facilitating signal detection and timing synchronization Improved beacon signaling methods are described. Beacon signals are transmitted on the same tone in at least two consecutive symbol periods facilitating accurate energy measurements over a symbol period even if timing synchronization with the transmitter is not main... | 05/10/2011 |
| 7939926 | Via first plus via last technique for IC interconnects A multi-tiered IC device contains a first die including a substrate with a first and second set of vias. The first set of vias extends from one side of the substrate, and the second set of vias extend from an opposite side of the substrate. Both sets of vias are cou... | 05/10/2011 |
| 7936596 | Magnetic tunnel junction cell including multiple magnetic domains In a particular embodiment, a magnetic tunnel junction (MTJ) structure is disclosed that includes an MTJ cell having multiple sidewalls that extend substantially normal to a surface of a substrate. Each of the multiple sidewalls includes a free layer to carry a uniq... | 05/03/2011 |
