Stoltz; Richard A., Kesterson; James C., Donaldson; Richard L. - US Patent Attorneys and Agents

Attorney: Stoltz; Richard A., Kesterson; James C., Donaldson; Richard L.

Number of patents: 34
Last date: July 14, 1998

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Number	Title	Issue Date
5781551	Computer communications system with tree architecture and communications method This is a method and system of communicating on a data and computer communications network. The method of communications for a data and computer communications network, wherein the network includes a master system board with a plurality of subsystem board...	07/14/1998
5647946	Structure and method including dry etching techniques for forming an array of thermal sensitive elements An array of thermal sensor elements (16) is formed from a pyroelectric substrate (46) having an infrared absorber and common electrode assembly (18) attached thereto. A first layer of metal contacts (60) is formed to define masked (61) and unmasked (68) r...	07/15/1997
5629074	Durable polymeric optical systems A polymeric infrared window (10) is described which comprises a sheet of polymeric material (14). Sheet 14 further may comprise a layer of molecular weave polymer material (34) fixed to a electromagnetic interference shield (32). In addition, a polymeric ...	05/13/1997
5352330	Process for producing nanometer-size structures on surfaces using electron beam induced chemistry through electron stimulated desorption The process of using electron beam induced stimulated desorption chemistry to produce structures of nanometer order size on surfaces. By passivating a reconstructed surface and selectively removing such passivation with an electron beam through the electr...	10/04/1994
5326721	Method of fabricating high-dielectric constant oxides on semiconductors using a GE buffer layer This is a method for fabricating a structure useful in semiconductor circuitry. The method comprises: growing a germanium layer 28 directly or indirectly on a semiconductor substrate 20; and depositing a high-dielectric constant oxide 32 (e.g. a ferroelec...	07/05/1994
5326711	High performance high voltage vertical transistor and method of fabrication A transistor device (10) includes an epitaxial layer (14) formed on a semiconductor substrate layer (12). A base layer (16) is formed on the epitaxial layer (14) and a source layer (18) is formed on the base layer (16). A trench region (22) is formed exte...	07/05/1994
5321401	Method and apparatus for digital to analog conversion with minimized distortion A digital to analog converter (10) and method is provided in which a plurality of digital to analog converter cells (16) generate an analog output signal based on a digital input signal, the cells being characterized by a switching threshold. An error sig...	06/14/1994
5321284	High frequency FET structure A GaAs field effect transistor with a source contact including both an ohmic contact and a Schottky barrier, the Schottky barrier between the ohmic contact and the gate, is disclosed. The Schottky barrier provides a high frequency source contact close to ...	06/14/1994
5320007	Method for positioning and processing LPE films A method and apparatus are provided for holding and positioning objects for a single diamond point turning operation. The objects which may include liquid phase epitaxy films are mounted on multiple platforms (10, 46). The platforms (10, 46) are securely ...	06/14/1994
5318918	Method of making an array of electron emitters This is a method of forming an array of electron emitters at the face of a semiconductor layer. The method comprises the steps of depositing a layer of polycrystalline silicon on a face of a semiconductor workpiece; doping the polycrystalline silicon laye...	06/07/1994
5318666	Method for via formation and type conversion in group II and group VI materials A method of forming an n-p junction in a body (44, 44a, 44b) formed of Group II and Group VI elements. The body (44, 44a, 44b) initially is of p-type conductivity characteristic, and a dry reactive etching process is employed for forming a via (60, 60a, 6...	06/07/1994
5316793	Directed effusive beam atomic layer epitaxy system and method A system and method for epitaxial growth of high purity materials on an atomic or molecular layer by layer basis wherein a substrate is placed in an evacuated chamber which is evacuated to a pressure of less than about 10-9 Torr and predetermin...	05/31/1994
5314651	Fine-grain pyroelectric detector material and method An improved pyroelectric material comprises a polycrystalline material doped with at least one donor element such that the polycrystalline material has a grain size less than 10 μm (or 5 μm) and a Figure of Merit greater than 90 nC/(cm2.K). I...	05/24/1994
5309088	Measurement of semiconductor parameters at cryogenic temperatures using a spring contact probe A system and method for testing the properties of semiconductor material including an enclosed chamber, a sample of semiconductor material under test having a polished surface portion and insulator layer over the polished surface portion supported in the ...	05/03/1994
5302539	VLSI interconnect method and structure A local interconnect system for VLSI integrated circuits. During self-aligned silicidation of exposed moat and gate regions in a nitrogen atmosphere, a conductive titanium nitride layer is formed overall. Normally this conductive layer is stripped to avoi...	04/12/1994
5300777	Two color infrared detector and method A two color infrared detector (10) is described comprising a heterojunction diode and a metal insulator semiconductor ("MIS") device. The diode comprises first (12) and second (14) semiconductor regions which are operable to generate electron-hole pairs w...	04/05/1994
5295091	Analog implementation of a pattern classifier A method of and system for classifying a pattern wherein there is provided a node, the negative of a predetermined threshold signal is applied to the node, a plurality of digital signals in parallel, is provided the digital signals are converted to analog...	03/15/1994
5294823	SOI BICMOS process This invention is an SOI BICMOS process which uses oxygen implanted wafers as the starting substrate. The bipolar transistor is constructed in two stacked epitaxial layers on the surface of the oxygen implanted substrate. A buried collector is formed in t...	03/15/1994
5290719	Method of making complementary heterostructure field effect transistors Complementary heterostructure field effect transistors (30) with complementary devices having complementary gates (40, 50) and threshold adjusting dopings are disclosed. Preferred embodiment devices include a p+ gate (50) formed by diffusion of...	03/01/1994
5286985	Interface circuit operable to perform level shifting between a first type of device and a second type of device Interface circuits for connecting gallium arsenide circuits with silicon circuits with the interface circuits using a mix of gallium arsenide and silicon devices. Preferred embodiments (200) connect gallium arsenide buffered FET logic circuits (202) with ...	02/15/1994
5285098	Structure and method internal photoemission detection A method and structure are provided for internal photoemission detection. At least one groove (30a) is formed in a side of a semiconductor layer (32). A silicide film (58) is formed in each groove (30a) over the semiconductor layer (32). A metal contact r...	02/08/1994
5277746	High pressure liquid phase epitaxy reactor chamber and method with direct see through capability An apparatus (10) and method are provided for directly viewing, through a viewport assembly (26), the process for forming a layer of mercury cadmium telluride of a predetermined composition on a surface of a wafer (not shown). According to the invention, ...	01/11/1994
5254850	Method and apparatus for improving photoconductor signal output utilizing a geometrically modified shaped confinement region A method and apparatus for improving photoconductor signal output is provided in which a photon collection aperture receives photons. Charge carriers are generated in response to the photons in a charge generation region. These charge carriers are conduct...	10/19/1993
5238869	Method of forming an epitaxial layer on a heterointerface Heteroepitaxy of lattice-mismatched semiconductor materials such as GaAs (110) on silicon (102) is accomplished by formation of a defect annihilating grid (104) on the silicon (102) prior to the epitaxy of the GaAs (110)....	08/24/1993
5225363	Trench capacitor DRAM cell and method of manufacture A plurality of trenches (26, 28) of a DRAM cell array formed in a (P-) epitaxial layer (11) and a silicon substrate (12), and storage layers (38, 40) are grown on the sidewalls (34, 36) and bottom (not shown) of the trenches (26, 28). Highly doped polysil...	07/06/1993
5217924	Method for forming shallow junctions with a low resistivity silicide layer A method for forming a shallow junction (56) with a relatively thick metal silicide (52) thereover is provided. A first relatively thin layer (38) of a metal is deposited over the surface of a semiconductor substrate. An impurity (40) is then implanted (4...	06/08/1993
5214298	Complementary heterostructure field effect transistors Complementary heterostructure field effect transistors (30) with complementary devices having complementary gates (40, 50) and threshold adjusting dopings are disclosed. Preferred embodiment devices include a p+ gate (50) formed by diffusion of...	05/25/1993
5202574	Semiconductor having improved interlevel conductor insulation A semiconductor device and method of manufacture employs an improved insulating layer to laterally separate conductive layers or regions. A relatively thick insulating layer is anistropically patterned to form an electrode having a thick insulating layer ...	04/13/1993
5202276	Method of forming a low on-resistance DMOS vertical transistor structure This is a DMOS transistor and a method of forming a DMOS transistor structure. The method comprises: forming a polycrystalline silicon central gate region; forming a drain region in the substrate self-aligned to the central gate region; forming polycrysta...	04/13/1993
5201989	Anisotropic niobium pentoxide etch A niobium pentoxide substrate 34 immersed in a liquid ambient (e.g. 10% hydrofluoric acid 30) and illuminated with radiation (e.g. collimated visible/ultraviolet radiation 24) produced by a radiation source (e.g. a 200 Watt mercury xenon arc lamp 20). A w...	04/13/1993
5199087	Optoelectronic integrated circuit for transmitting optical and electrical signals and method of forming same A package receives and encapsulates an optoelectronic integrated circuit chip. A plurality of optically transmissive filaments have first ends coupled with the chip and second ends opposite the first ends positioned outside the package. In a preferred emb...	03/30/1993
5198372	Method for making a shallow junction bipolar transistor and transistor formed thereby Disclosed is a process for forming a bipolar transistor at the face (22) of a semiconductor layer. A refractory metal layer (34) is deposited on the face (22) to cover a base area (38) thereof. A dopant (40) is implanted through the metal layer (34) withi...	03/30/1993
5196359	Method of forming heterostructure field effect transistor A heterostructure field effect transistor having a buffer layer comprising a first compound semiconductor material. A layer of second semiconductor material different from the first material is formed over the buffer layer. The second layer has a total th...	03/23/1993
5192706	Method for semiconductor isolation This is a method of forming a semiconductor integrated circuit with isolation regions, (possibly wide and narrow) comprising of a thin oxide film and deposited anisotropic oxide. It uses an inorganic layer (e.g. noncrystalline silicon) to mask what will b...	03/09/1993

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Attorney: Stoltz; Richard A., Kesterson; James C., Donaldson; Richard L.