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| Number | Title | Issue Date |
| 7573307 | Systems and methods for reduced area delay locked loop Various systems and methods for signal synchronization are disclosed. For example, some embodiments of the present invention provide methods for reduced area delay signal timing. Such methods include providing a delay lock loop circuit with a plurality of selectable... | 08/11/2009 |
| 7515392 | High voltage circuits implemented using low voltage transistors Transistors of low voltage specification are used to process information in a signal received at a high(er) voltage level. A protection circuit ensures that the cross terminal voltages do not exceed an allowed maximum voltage (e.g., 2.4 V for transistors of 1.8V spe... | 04/07/2009 |
| 7511552 | Method and apparatus of a level shifter circuit having a structure to reduce fall and rise path delay A method, apparatus and/or system of a level shifter circuit having a structure to reduce fall and rise path delay is disclosed. In one embodiment, a level shifter circuit comprise a first set of sequentially coupled pull-up and pull-down sub-circuits cross coupled ... | 03/31/2009 |
| 7508728 | Methods and apparatus to provide refresh for global out of range read requests Methods and apparatus to provide refresh when an out of range address is received are disclosed. An example method of providing a refresh signal to a memory cell includes receiving a memory address on address lines ranging from a most significant bit address line to... | 03/24/2009 |
| 7498879 | Summing comparator for higher order class D amplifiers The summing comparator includes: a first integrator; a second integrator for receiving an output of the first integrator; and a comparator for switching when the output of the first integrator is greater than the output of the second integrator. The outputs of the f... | 03/03/2009 |
| 7496154 | Power and area efficient receiver circuit having constant hysteresis for noise rejection A hysteresis receiver containing two inverters and a logic controller. The inverters are implemented with threshold voltages equaling Vil and Vih, which together define the hysteresis window. The inverters receive the input signal and generate a respective inverted ... | 02/24/2009 |
| 7494829 | Identification of outlier semiconductor devices using data-driven statistical characterization Systems and methods for identification of outlier semiconductor devices using data-driven statistical characterization are described herein. At least some preferred embodiments include a method that includes identifying a plurality of sample semiconductor chips that... | 02/24/2009 |
| 7487417 | Digital storage element with enable signal gating A digital storage element (e.g., a flip-flop or a latch) comprise a master transparent latch that receives functional data from a data input port and scan data from a scan input port and a slave transparent latch coupled to the master transparent latch. The slave tr... | 02/03/2009 |
| 7483819 | Representing data having multi-dimensional input vectors and corresponding output element by piece-wise polynomials Determining piece-wise polynomials which together would represent large data sets having multi-dimensional input vectors and corresponding output element. In an embodiment, a function/procedure/routine is recursively called/invoked to determine piece-wise polynomial... | 01/27/2009 |
| 7471536 | Match mismatch emulation scheme for an addressed location in a CAM A novel match/mismatch emulation scheme for an addressed location in a CAM system that includes a plurality of CAM blocks. The plurality of CAM blocks are organized into at least one rectangular array having rows each having a plurality of CAM blocks, a group of CAM... | 12/30/2008 |
| 7468500 | High performance charge detection amplifier for CCD image sensors The CCD charge detection amplifier includes a floating diffusion charge detection node biased from a voltage reference node; a reset device coupled between the floating Diffusion charge detection node and the voltage reference node; a first source follower stage hav... | 12/23/2008 |
| 7466576 | Technique for CAM width expansion using an external priority encoder A technique that provides width expansion of two CAMs of varying widths by combining match results from two CAMs by integrating the two CAMs. In one embodiment, a synchronizer circuit triggers the operation of an External Priority Encoder module which can be used to... | 12/16/2008 |
| 7443217 | Circuit and method to balance delays through true and complement phases of differential and complementary drivers A circuit for balancing delays through true and complement phases of complementary drivers includes: a first driver; a second driver; a first delay device coupled to an input of the first driver and having an input coupled to an input signal node; a second delay dev... | 10/28/2008 |
| 7443331 | Multiple-bank CMOS image sensor system and method A CMOS image sensor system includes first and second groups of CMOS sensors each responsive to periodic first and second clock signal edges, the second clock signal edge being out-of-phase with the first clock signal edge. Output signals of the first group of CMOS s... | 10/28/2008 |
| 7443935 | Apparatus and method for dynamically adjusting receiver bandwidth An apparatus for adjusting bandwidth for a receiver includes: (a) a receiver clock operating according to receiver clock parameters related to received signals for sampling received signals; (b) a local clock; (c) a tracker receiving an indicator related to the rece... | 10/28/2008 |
| 7443913 | High speed decision feedback equalizer An equalizer comprises a sampler, a filter, and a summer. The sampler samples a signal indicative of an input communication signal to determine digital decision output signals having a communication device data rate. The filter receives digital decision output signa... | 10/28/2008 |
| 7439796 | Current mirror with circuitry that allows for over voltage stress testing A current mirror circuit that allows for over voltage stress testing includes: a first transistor; a second transistor having a gate coupled to a gate of the first transistor; a switch coupled between the gate of the first transistor and the drain of the first trans... | 10/21/2008 |
| 7409415 | Processor system with efficient shift operations including EXTRACT operation An electronic system (2001) for manipulating an input data argument (D[31:0]) comprising an integer number of bits. The system comprises an input (R) for receiving a right direction argument and an input (L) for receiving a left direction argument.... | 08/05/2008 |
| 7385440 | Bootstrapped switch for sampling inputs with a signal range greater than supply voltage A bootstrapped circuit for sampling inputs with a signal range greater than supply voltage includes: a bootstrapped switch coupled between an input node and an output node; a first transistor coupled to a control node of the bootstrapped switch; a first capacitor ha... | 06/10/2008 |
| 7379354 | Methods and apparatus to provide voltage control for SRAM write assist circuits Methods and apparatus to control voltage output of a write assist circuit are disclosed. An example method includes regulating pull down voltage from a write assist circuit having a write assist capacitor coupled to a discharge node coupled to a bit line. The write ... | 05/27/2008 |
| 7380185 | Reduced pin count scan chain implementation The synchronous logic device with reduced pin count scan chain includes: more than two flip/flops coupled to form a shift register for receiving a scan data input signal; a combinational logic circuit for receiving device inputs, generating flip/flop inputs for the ... | 05/27/2008 |
| 7380184 | Sequential scan technique providing enhanced fault coverage in an integrated circuit According to an aspect of the present invention, multiple scan enable signals (controlling corresponding scan chains) are used in an integrated circuit, and the scan chains are placed in evaluation mode in non-overlapping durations between scan-in and scan-out opera... | 05/27/2008 |
| 7376871 | CAM test structures and methods therefor Configurations and methods that enable the testing of CAM-specific circuitry, even if the memory is defective, are implemented by utilizing various test modes. Accordingly, the CAM can be debugged to isolate memory failures from priority encoder failures, which sign... | 05/20/2008 |
| 7375567 | Digital storage element architecture comprising dual scan clocks and preset functionality A digital storage element comprising a master transparent latch that receives functional data from a data input port and scan data from a scan input port and comprises a master feedback loop with a first transistor coupled to the master feedback loop. The first tran... | 05/20/2008 |
| 7376211 | High speed early/late discrimination systems and methods for clock and data recovery receivers The present invention facilitates clock and data recovery for serial data streams by providing a mechanism that can be employed to detect and adjust operation and timing of clocks. The invention employs a differential analog circuit, using current steering logic, to... | 05/20/2008 |
| 7372713 | Match sensing circuit for a content addressable memory device A Content Addressable Memory (CAM) device with an improved match sensing circuit is provided. The CAM is provided with a dummy cell and a respective dummy match line, as well as a reference dummy match line. The dummy match line is designed to be evaluated after all... | 05/13/2008 |
| 7352228 | Method and apparatus of a level shifter circuit with duty-cycle correction A method and/or a system of control signal synchronization of a scannable storage circuit is disclosed. In one embodiment, a system includes a first circuit to operate based on a first voltage of a first power supply, a second circuit to operate based on a second vo... | 04/01/2008 |
| 7349932 | High performance FIR filter A filter includes a tap multiplication circuit and a tap digital-to-analog (“DAC”) unit coupled to the tap multiplication circuit. Further, a plurality of clocks are provided that control timing associated with the tap multiplication circuit and that permit one ... | 03/25/2008 |
| 7349934 | Processor system and method with combined data left and right shift operation An integrated circuit device (100) includes circuitry for providing a first shift argument (L[4:0]) indicating shift positions in a first direction and circuitry for providing a second shift argument (R[4:0]) indicating shift positions in a second direction. ... | 03/25/2008 |
| 7349285 | Dual port memory unit using a single port memory core A dual port memory implemented using a single port memory core. In an embodiment, the access requests from the two ports are processed in a single memory clock cycle. In one implementation, the access request corresponding to the first port is processed in the high ... | 03/25/2008 |
| 7345518 | Digital storage element with dual behavior A digital storage element comprises a master transparent latch that receives functional data from a data input port and scan data from a scan input port and a slave transparent latch coupled to the master transparent latch. The slave transparent latch comprises dedi... | 03/18/2008 |
| 7346731 | High performance and scalable width expansion architecture for fully parallel CAMs A technique that provides highly scalable width expansion architecture for cascading CAMs to facilitate searching of increased wordlengths. In one example embodiment, this is achieved by combining a plurality of CAM devices in a serial cascade arrangement. Each CAM ... | 03/18/2008 |
| 7345529 | Chopper stabilized amplifier without DC output ripple The chopper stabilized amplifier circuit includes: an amplifier; a first current mirror coupled to an output of the amplifier through a first switch; a second current mirror coupled to the output of the amplifier through a second switch, wherein the first switch is ... | 03/18/2008 |
| 7318112 | Universal interface simulating multiple interface protocols A universal interface interfaces between a variety of different data processing devices by the generation, storage, proper routing, and timed output of data signals to simulate behavior of a traditional interface device dedicated to that particular communications pr... | 01/08/2008 |
| 7315191 | Digital storage element architecture comprising dual scan clocks and reset functionality A digital storage element comprising a master transparent latch that receives functional data from a data input port and scan data from a scan input port and comprises a master feedback loop with a first transistor coupled to the master feedback loop. The first tran... | 01/01/2008 |
| 7315182 | Circuit to observe internal clock and control signals in a receiver with integrated termination and common mode control A serial data receiver circuit includes a pair of differential input nodes, and receiver circuitry and a termination circuit coupled between the differential input nodes. The termination circuit comprises a common mode node. A common mode control circuit is connecte... | 01/01/2008 |
| 7315806 | Enhanced negative constraint calculation for event driven simulations A technique to enable accurate timing and functional verification in a negative constraint calculation (NCC) implemented event-driven logic simulators when there are negative constraints in logic elements. In one example embodiment, the technique adjusts negative ti... | 01/01/2008 |
| 7315992 | Electro-migration (EM) and voltage (IR) drop analysis of integrated circuit (IC) designs Performing approximate analysis of modules based on corresponding layout files while requiring fewer computations than performing a transistor level simulation of a design of a module or integrated circuit. One feature enables IR/voltage drop and EM (electro migrati... | 01/01/2008 |
| 7315596 | Interpolator based clock and data recovery (CDR) circuit with digitally programmable BW and tracking capability The present invention facilitates clock and data recovery (330,716/718) for serial data streams (317,715) by providing a mechanism that can be employed to maintain a fixed tracking capability of an interpolator based CDR circuit (300,700) at mul... | 01/01/2008 |
| 7315540 | Random access memory based space time switch architecture A data switching circuit (10). The data switching circuit comprises at least one input (10in) for receiving during a same time period a plurality of data streams (ICH0-ICH127). Each of the data streams comprises a plurality of ... | 01/01/2008 |
