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| Number | Title | Issue Date |
| 6408017 | High speed demux parallel correlator system In a high speed, high processing gain PN spread spectrum acquisition system an analog signal comprising a high speed PN code is received and converted to a high speed digital format. A demuxer is employed to divided the high speed digital signal into lowe... | 06/18/2002 |
| 6404362 | Method and apparatus for reducing the time required for decompressing compressed data In a data decompression system of the type having a self-compiling dictionary for building or replicating codes used for decoding incoming code values, there is provided a decoded string dictionary or memory for storing plural characters representing deco... | 06/11/2002 |
| 6401133 | System for high speed continuous file transfer processing of data files In a system for economically and continuously transmitting data files from one location to a remote location there is provided a high speed mainframe computer adapted to read a data file and to determine if the process to be performed on the data requires... | 06/04/2002 |
| 6320523 | Method and apparatus for reducing the time required for compressing data The present invention provides a novel method and system for obtaining maximum system speed performance for compressing coded data characters in a serial data stream by replacing strings of data with code values stored in a dictionary when strings are fir... | 11/20/2001 |
| 6321198 | Apparatus for design and simulation of dialogue A novel dialogue design system is provided for creating dialogue applications of the type understood and used by automatic speech recognition systems. The dialogue design system is loaded into a computer having a display and a control keyboard and compris... | 11/20/2001 |
| 6006296 | Scalable memory controller A single ASIC memory controller has full interconnectivity between various modes on the ASIC: input controller, memory controller, and output controller. The single ASIC includes an input controller section, a memory controller section, and an output cont... | 12/21/1999 |
| 5757817 | Memory controller having automatic RAM detection A system and method for automatically detecting the presence and configuration (e.g., number of rows and columns) of a writable memory module. A first data pattern is written to a first memory location. One or more data patterns different from the first d... | 05/26/1998 |
| 5502745 | BPSK modulator for a digital signal transmitter An improved digital data modulator is provided for a digital transmitter. The digital data modulator comprises of a pair of digital data synthesizers which are controlled in a manner which produces complex conjugate modulated data signals of the input sig... | 03/26/1996 |
| 5485484 | Digitally implemented phase and lock indicators for a bit synchronizer A bit synchronizing circuit is provided with both analog and digital devices in an enhanced bit synchronizing circuit system. There is provided a digital phase detector and a digital lock detector which are compatible with analog circuity. The output of t... | 01/16/1996 |
| 5452327 | Programmable randomly tunable digital demodulator A programmable randomly tunable digital demodulator is provided with a carrier recovery loop and a PN code clock recovery loop each having a programmable digital loop filter coupled in series therein. Each digital loop filter is controlled by a timing con... | 09/19/1995 |
| 5442644 | System for sensing the state of interconnection points A system for sensing the state or condition of a very large number of interconnection points in real time in electrical context with other points in a system. The system has a plurality of multiple interconnect sense modules having a plurality of intercon... | 08/15/1995 |
| 5432813 | Parallel processing based digital matched filter and error detector for a digital demodulator A high chipping rate digital demodulator circuit is coupled to the output of an analog front end communications receiver and comprises a low pass filter in each channel of the receiver. The filtered output is coupled to a plurality of parallel branches ea... | 07/11/1995 |
| 5414730 | Asynchronous samples data demodulation system A novel PN code acquisition and demodulation circuit comprise an analog receiver coupled to an analog to digital converter. The digital output of the converter is passed through an N chip width parallel correlator. The parallel outputs are coherently accu... | 05/09/1995 |
| 5408631 | Interface unit circuit with on-chip test simulation A novel interface unit circuit for connecting circuit card assemblies to a data stream and to each other is designed for implementation on a high speed semiconductor chip. A parallel bit data word comprising a programmable address field is compared to a m... | 04/18/1995 |
| 5315633 | Digital video switch for video teleconferencing A digital video switch system comprising a smart control terminal is coupled to a digital access controller and to a multipoint control unit. The smart control terminal is provided with a plurality of function keys, each of which is designed to provide au... | 05/24/1994 |
| 5300931 | Memory based vector quantization Apparatus is provided for performing two stages of high-speed compression of vector data inputs. Two input channels of vector data are compressed and encoded through a vector quantizer encoder to provide a first stage of data compression. The output of th... | 04/05/1994 |
| 5298908 | Interference nulling system for antennas An interference nulling system is provided which nulls out all types of interference signals received in different lobes of the receiving antenna. The data to be received is transmitted from a high quality circular polarized transmitter antenna having the... | 03/29/1994 |
| 5299229 | High rate-low rate PN code tracking system A high PN code rate receiving system is provided for receiving, recovering and tracking a high rate PN composite code comprising a low rate PN code combined with a high rate PN code and wherein the receiving system comprises a broad band receiver for rece... | 03/29/1994 |
| 5257319 | Character recognition apparatus A character recognition apparatus uses a magnetic head to read magnetic printed coded characters from a passing cheque 10. A head 24 using a circuit including a delay line 58 drives a controller 76 which, should a character not instantly be recognized by ... | 10/26/1993 |
| 5257282 | High speed code sequence generator A novel low speed code sequence generator having a set of parallel flip-flops is provided and comprises a vector generator in series between the outputs and the inputs of the set of parallel flip-flops in the generator. The outputs from the low speed code... | 10/26/1993 |
| 5222100 | Range based acquisition system A novel range based acquisition system includes a receiver for receiving PN encoded signals coupled to a novel range based variable dwell correlator which detects and acquires uniquely timed received transmitter PN encoded signals employing different sear... | 06/22/1993 |
| 5213416 | On chip noise tolerant temperature sensing circuit A novel on-chip temperature sensing circuit includes a differential voltage source which comprises a plurality of branches each of which is provided with temperature sensitive transistor means. The differential output from the differential voltage source ... | 05/25/1993 |
| 5197729 | Document transport track drive mechanism An improved document transport track drive system for a document processing machine for driving a document 10 along a track 12. The drive mechanism comprises a common drive motor 20 driving a drive shaft 30 arranged parallel to the plane of the documents ... | 03/30/1993 |
| 5179691 | N-byte stack-oriented CPU using a byte-selecting control for enhancing a dual-operation with an M-byte instruction word user program where M An apparatus for enhancing the operation of a M byte instruction word CPU when operating user programs on an N byte instruction word CPU. The M-Byte instruction word CPU is provided with an N-Byte instruction register and a main memory for supplying N-Byt... | 01/12/1993 |
| 5175835 | Multi-mode DRAM controller The present invention provides a novel multi-mode DRAM controller adaptd to access DRAM chips of a main storage unit of different size and of different mode types. The novel DRAM controller comprises new address generation and control logic for delaying t... | 12/29/1992 |
| 5151952 | Character recognition apparatus which obtains distance ratios between edges in a character for identification An apparatus for recognizing characters 20 on a document 10 comprises a scanning head 24 and decoding circuits 78, 72, 86, 92, 80, feeding a controller 84. The controller 84 detects the identity of the characters 20A-20N by calculating the ratio found by ... | 09/29/1992 |
| 5128958 | Digital time error signal generator A time error signal generator of the type employed in symbol time tracking loops is provided with a pre-accumulate and scale circuit for receiving an input data stream which is applied to a digital early sample-late sample circuit for generation an error ... | 07/07/1992 |
| 5105437 | Programmable digital acquisition and tracking controller A novel programmable digital acquisition and tracking controller is coupled to the input signal level from the demodulator of a communications receiver and provides programmable signal level threshold detectors and detection intervals adapted to produce a... | 04/14/1992 |
| 5101356 | Moving vehicle attitude measuring system A system for determining attitude of airborne vehicles or surface vehicles is provided with three fixed position antennas separated from each other by a predetermined calibrated distance. Each antenna is connected to a GPS receiver and the receiver output... | 03/31/1992 |
| 5101370 | Programmable digital accumulate and scale circuit A novel accumulate and scale circuit is provided with an input accumulator which is only as wide as the input data stream. Additional most significant bits are generated to extend the output of the accumulate and scale circuit by providing and an up and d... | 03/31/1992 |
| 5099494 | Six channel digital demodulator A six channel programmable digital demodulator of the type designed to be manufactured as an integrated circuit with other components comprises a code channel, a level channel and a phase channel each of which includes two accumulate and scale circuits. E... | 03/24/1992 |
| 5093906 | Text orientation system for dot matrix printers A text orientation system for dot matrix printers includes a character adjust logic for orienting an image to be printed relative to a physical page. A first register in the character adjust logic receives a word of memory for either placement or characte... | 03/03/1992 |
| 5088025 | Input/output processor control system with a plurality of staging buffers and data buffers A control system for multiple channel data transfers between a main bus and a data bus is provided. A novel input/output processor control which permits multiple word transfers to occur in a single predetermined time slot while resolving buffer access con... | 02/11/1992 |
| 5084913 | Programmable multi-mode two-channel timing generator A novel universal multi-mode programmable two-channel timing generator employs a plurality of counters and logic circuitry. An input chip counter is coupled for receiving system clock signals and producing chip strobe and other output timing signals which... | 01/28/1992 |
| 5081700 | Apparatus for high speed image rotation Apparatus for shifting the output of a bit matrix character generator ninety degrees to provide ninety degrees shifted characters and comprises a barrel shifter for barrel shifting bit slices of the bit matrix characters coupled to a linear array shifter ... | 01/14/1992 |
