"The wireless music box has no imaginable commercial value. Who would pay for a message sent to nobody in particular?"
David Sarnoff, American radio pioneer ; 1921
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| Number | Title | Issue Date |
| 5832310 | Serial I/O channel having dependent and synchronous sources of control data and user defined data Apparatus is provided for transferring user defined data from a parallel storage medium to a serial link driver in an I/O channel subsystem of a processor or I/O device controller. The serial link driver transmits a frame of user defined data over a seria... | 11/03/1998 |
| 5787153 | System for incremental redistribution of telephony applications computing workload Disclosed is a telephony messaging transfer system permitting a messaging host to redistribute its processing and/or storage load to another messaging host. An administrator can dynamically control the amount of time needed to transfer specified mailboxes... | 07/28/1998 |
| 5778004 | Vector translator A technique for accepting test vectors in one format, generally proven to operate correctly, from an IC tester such as the Logic Master XL2 ("off-bench tester") and processing/converting them into another format for use in a stimulus generator such as the... | 07/07/1998 |
| 5717897 | System for coordinating coherency of cache memories of multiple host computers of a distributed information system Apparatus and method for coordinating cache coherency between host cache memories in a distributed information system in a system which comprises at least one main storage memory coupled to a plurality of host computers through controllers. Each host comp... | 02/10/1998 |
| 5704052 | Bit processing unit for performing complex logical operations within a single clock cycle A microprocessor architecture that includes an arithmetic logic unit (ALU), a bit processing unit (BPU), a register file and an instruction register is disclosed. The BPU performs complex logical operations in a single clock cycle. The ALU continues to pe... | 12/30/1997 |
| 5699505 | Method and system for automatically collecting diagnostic information from a computer system A method is provided for collecting information located within a plurality of hardware elements of a computer system. The hardware elements of the plurality of hardware elements are simultaneously instructed to collect the information. The information wit... | 12/16/1997 |
| 5696936 | Low latency message processor interface using memory mapped Read/Write Windows A low latency software and hardware interface between a microprocessor and Network Interface Unit is disclosed. The Network Interface Unit interfaces to the microprocessor's Level 2 cache interface, which provides burst transfers of cache lines between th... | 12/09/1997 |