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| Number | Title | Issue Date |
| 5758335 | Optimizing table join ordering using graph theory prior to query optimization A method for improving the efficiency of queries in relational database management systems that use the exhaustive method of query optimization. The join structure of the query is examined prior to query optimization and tables are ordered according to gr... | 05/26/1998 |
| 4862354 | Multiprocessor system with interrupt notification and verification unit A multiprocessor system architecture in which two processors are each provided with an autonomous bus and the two buses can be selectively connected to each other to form a unique system bus which enables access by all processors to common memory resource... | 08/29/1989 |
| 4862462 | Memory systems and related error detection and correction apparatus Memory system and related error detection and correction apparatus wherein the memory, independently on its parallelism, is organized in modules having single byte parallelism, each module having a section with a plurality of bit parallelism for storing S... | 08/29/1989 |
| 4850724 | Control circuit for dot matrix printing head Control circuit for a dot matrix printing head of the permanent magnetic type or simple electromagnet type, wherein a printing element is subjected to a variable magnetic flux, owing to an energization current and/or to a movable armature movement, which ... | 07/25/1989 |
| 4823262 | Apparatus for dynamically switching the clock source of a data processing system A data processing system includes a first and a second central system wherein the central processing unit (CPU) of the first central system is operatively connected to the system control unit (SCU) of the second central system and the CPU of the second ce... | 04/18/1989 |
| 4767104 | Non-precious metal furnace with inert gas firing A furnace for firing a non-precious metal paste including organic material, comprising a furnace enclosure, tube-like in shape, having a definable length. First and second ends of the furnace enclosure is open forming an entrance and exit, respectively. A... | 08/30/1988 |
| 4707784 | Prioritized secondary use of a cache with simultaneous access Cache memory includes a dual or two part cache with one part of the cache being primarily designated for instruction data while the other is primarily designated for operand data, but not exclusively. For a maximum speed of operation, the two parts of the... | 11/17/1987 |
| 4695923 | Printed circuit board bolt-on power distribution system A bolt-on configuration of a power distribution system utilizes an apparatus which connects a first element to a second element, the second element having a hole, such that a minimum predetermined force exists at the connection between the first element a... | 09/22/1987 |
| 4695951 | Computer hierarchy control A multiple processor computer system features a store-into cache arrangement wherein each processor unit of the system has its own unique cache memory unit. Data operated upon by any one of the processor units is stored in the cache memory associated with... | 09/22/1987 |
| 4694241 | Transformer tap changer One of a plurality of taps of at least one transformer is selected by choosing a predetermined plug to mate with a predetermined jack. The connection arrangement between each transformer and a corresponding jack is such that each pin of a respective jack ... | 09/15/1987 |
| 4688186 | Division by a constant by iterative table lookup A bit-string address or a multi-bit character count is converted to a real word memory address by division by a constant value. The division is accomplished without reference to an arithmetic logic unit. Division is accomplished by means of a look-up tabl... | 08/18/1987 |
| 4680702 | Merge control apparatus for a store into cache of a data processing system A register unit includes means for storing pertinent data relative to a plurality of cache transactions, identifying the zones of an addressed word block which is the subject of the individual transactions. These data are selectively extracted from the re... | 07/14/1987 |
| 4670876 | Parity integrity check logic A computer system includes at least on error detecting circuit for checking data bits and an associated check bit to verify that the data does not contain an error. An apparatus for verifying the operation of the error detection circuit comprises a genera... | 06/02/1987 |
| 4665822 | Squeegee for screen process printers for printing of dielectric and metallic pastes for single and multilayer hybrid circuits A squeegee is utilized in a screen process printer for microcircuits and components thereof. The type is one in which the squeegee and a flat stationary screen are mounted with the squeegee movable and in a wiping action makes contact with the screen so a... | 05/19/1987 |
| 4662067 | Apparatus and method for providing orientation of a coax cable having a ground termination bar A connector for providing electrical connections for a coax cable harness, the coax cable harness including a plurality of coax cables, each coax cable having a wire encased in a dielectric and having a drain wire. The connector comprises an insulation di... | 05/05/1987 |
| 4649539 | Apparatus providing improved diagnosability An apparatus for storing information contained in a selected digital data signal comprises a selector. A first input terminal receives an operational digital data signal when the apparatus is operating in a normal mode, a second input terminal receives a ... | 03/10/1987 |
| 4646304 | Single error correction circuit for system memory An improved single error correction circuit for a system memory storing in each of its addressable locations a data word and a corresponding error correcting code, which when read out from memory are fed to a syndrome generator which generates in output a... | 02/24/1987 |
| 4631695 | Detector of predetermined patterns of encoded data signals A detector of predetermined patterns of Manchester encoded data signals in which the voltage levels of the half-bit cells of "n" sequential Manchester bit cells, where "n" is an integer greater than zero, are clocked into a shift register, the pattern of ... | 12/23/1986 |
| 4631733 | Transceiver A transceiver for applying signals to and receiving signals from a transmission line through a coupling transformer having a transmission line winding connected to the transmission line and a transceiver winding. A transmitter circuit is connected to the ... | 12/23/1986 |
| 4628489 | Dual address RAM In a computer system, a memory system has a memory structure and means whereby the smallest memory unit, the RAM chip, may be addressed and accessed twice during each clock cycle.... | 12/09/1986 |
| 4625312 | Test and maintenance method and apparatus for investigation of intermittent faults in a data processing system A test and maintenance system for use with a data processing system comprising a specialized circuit set wherein the circuit set registers can be configured into a serial array, a clock signal distribution system capable of delivering controlled clock sig... | 11/25/1986 |
| 4620274 | Data available indicator for an exhausted operand string The present invention relates to an apparatus for providing a data available indication while inhibiting the reading of operand data beyond the last word of an operand data string. The data available indication operates to enable additional cycles to be g... | 10/28/1986 |
| 4612635 | Sequential data transmission system The present invention relates to a data transmission system, for transmitting information from a first end-user device to a second end-user device, which comprises a plurality of channel elements, each channel element having an input and an output termina... | 09/16/1986 |
| 4612542 | Apparatus for arbitrating between a plurality of requestor elements An arbitration circuit comprises a plurality of enabling elements which determines when predetermined conditions exist to transmit a request signal. A first gate combines transmitted request signals to generate a combined request signal. A plurality of fi... | 09/16/1986 |
| 4611278 | Wraparound buffer for repetitive decimal numeric operations The present invention relates to the operational control of a digital computer system which includes the digital logic circuitry for temporarily storing results internal to an execution unit. An input unit of the execution, which inputs operand words to t... | 09/09/1986 |
| 4610001 | Write amplifier A write amplifier for a computer memory unit features a first and a second output terminal. The amplifier may be controlled, in the write mode, to provide output signals, on the two output terminals, of one relative polarity or the other in accordance wit... | 09/02/1986 |
| 4608633 | Method for decreasing execution time of numeric instructions The present invention relates to a method within a digital computer system for reading operand data stored in a temporary storage memory in a forward or reverse direction. The method includes loading the temporary storage memory with the first and second ... | 08/26/1986 |
| 4607325 | Discontinuous optimization procedure modelling the run-idle status of plural process components A method of optimizing the operation of a process so that desired products are produced at minimum cost. The process has a plurality of process components, with each component having a run status and an idle status. The process has available more than one... | 08/19/1986 |
| 4607256 | Plant management system A plant management system is provided. The system includes one or more digital process control and data acquisition subsystems and a plant control network. Each control subsystem includes a data highway, and process control, and process interface units. T... | 08/19/1986 |
| 4602368 | Dual validity bit arrays An associative memory used to translate a virtual page number (VPN) of a virtual word address to a physical page number (PPN) of a physical word address of a random access memory of a digital computer system is provided with a pair of independently addres... | 07/22/1986 |
| 4598365 | Pipelined decimal character execution unit The present invention relates to an execution unit of a computing system which executes data manipulation type instructions and arithmetic type instructions on data words having a plurality of decimal character-type data formats. The pipelined execution u... | 07/01/1986 |
| 4598359 | Apparatus for forward or reverse reading of multiple variable length operands The present invention relates to an operational control of a digital computer system for reading operand data stored in a temporary storage memory in a forward or reverse direction. The present invention includes an adder for adding the current read addre... | 07/01/1986 |
| 4598212 | Driver circuit A driver circuit for applying a first signal having a desired wave form, frequency and peak to peak voltage to a coaxial transmission line which also has applied to it a second signal having a substantially higher frequency. An operational amplifier has t... | 07/01/1986 |
| 4597044 | Apparatus and method for providing a composite descriptor in a data processing system In a data processing system including a central processing unit capable of operation with a plurality of operating systems, a VMSM unit is described for producing a composite decor descriptor from a plurality of possible decor descriptor formats. The VMSM... | 06/24/1986 |
| 4594656 | Memory refresh apparatus A memory refresh control scheme is provided wherein the refresh timing and address signals are independent of memory configuration or the configuration of an interface unit. Since the system relates to a distributed memory arrangement, the refresh control... | 06/10/1986 |
| 4594659 | Method and apparatus for prefetching instructions for a central execution pipeline unit Method and apparatus for prefetching instructions for a pipelined central processor unit for a general purpose digital data processing system. A table is maintained for purposes of predicting the target addresses of transfer and indirect instructions base... | 06/10/1986 |
| 4593349 | Power sequencer A peripheral power control sequencer incorporates a microcomputer to control the sequencing of the powering of a plurality of peripheral control units. The terminals of the input/output ports of the microcomputer are time-shared to accommodate the several... | 06/03/1986 |
| 4593390 | Pipeline multiplexer A pipelined multiplexer is provided for selecting one-of-m input signals, comprising N stages of select elements, each stage of the select elements including 2n /2 select gates, where n is the stage number. Each select gate has two input termin... | 06/03/1986 |
| 4591842 | Apparatus for controlling the background and foreground colors displayed by raster graphic system Apparatus for controlling the colors displayed by a raster graphic system. Information stored at each addressable location of a RAM includes a set of behavior bits and a set of control bits. These bits are read out of memory during each memory read cycle.... | 05/27/1986 |
| 4583865 | Real time clock synchronization A method of synchronizing a digital timer with the frequency of a source of A.C. power to provide long term temporal stability. The timer produces internal, fine resolution, synchronization and real time timing signals from a source of clock signals. The ... | 04/22/1986 |
