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| Number | Title | Issue Date |
| 7400543 | Metal programmable self-timed memories A self-timed memory array is disclosed, in which segmentability and metal-programmability are supported while minimizing layout space. Self-timing row decoder circuits are placed at the top and bottom of the array adjacent to respective I/O blocks. A self-timing sig... | 07/15/2008 |
| 6725018 | Signal improvement by predistortion/postdistortion of programmable converter In accordance with the present invention, a communications system transmits a predetermined signal, from a first, sending, end of a communications system to a second, receiving, end of a communications system. The predetermined signal is distorted by the communicati... | 04/20/2004 |
| 6683465 | Integrated circuit having stress migration test structure and method therefor A stress migration test structure is provided that can be used to detect stress migration defects in traces or conductors of integrated circuits. The stress migration test structure can be placed between die areas on a wafer, or on a die. On the die, a st... | 01/27/2004 |
| 6640324 | Boundary scan chain routing An integrated circuit includes a semiconductor die having a plurality of input/output pads and a plurality of boundary scan cells. Each of the boundary scan cells includes a TDI input and a TDO output. A first boundary scan cell is the first boundary scan... | 10/28/2003 |
| 6507317 | Retractable antenna for electronic devices An electronic device having a retractable antenna is disclosed. The antenna is spring loaded and extends beyond the profile of the housing of the electronic device when in use. The antenna is retracted to within the profile of the housing of the electroni... | 01/14/2003 |
| 6449629 | Three input split-adder An integrated circuit includes an adder having a first adder circuit for receiving a portion of the operands to be summed, along with corresponding carry-in inputs. The first adder circuit provides a sum output and carry-out outputs. A second adder circui... | 09/10/2002 |
| 6407645 | Automated voltage control oscillator tuning There is disclosed a first stub short bonded across conductive runners of a tuning stub at a distance preferably greater than a distance resulting in the desired frequency of operation of a voltage controlled oscillator tuned by the tuning stub. Thereafte... | 06/18/2002 |
| 6404364 | Multistage converter employing digital dither A multistage converter and method for converting a sampled analog signal to a corresponding digital representation. Each stage of the converter receives an analog input signal and produces a partial digital output. A first stage receives the sampled analo... | 06/11/2002 |
| 6400208 | On-chip trim link sensing and latching circuit for fuse links An integrated circuit includes a pulse generator for generating a pulse of a predetermined duration. A first switch, controlled by the pulse, drives current into a fuse link when the pulse takes on a first logic level. The first switch prevents flow of cu... | 06/04/2002 |
| 6329877 | Efficient power amplifier There is disclosed a power amplifier includes an in-phase power splitter generating two split signals from an input signal, and two amplifiers capable of operating in different modes. The split signals are provided as respective inputs to the two amplifie... | 12/11/2001 |
| 6278393 | Multiple output digital-to-analog converter There is disclosed an integrated circuit including a digital-to-analog converter in which a resistor string is adapted to be coupled to a reference source. The resistor string includes a plurality of serially coupled impedances defining intermediate taps ... | 08/21/2001 |
| 6272188 | Single-cycle accelerator for extremun state search The invention includes a method of identifying an extremum value and an index in a group of values where each value has an associated index. A count register is initialized to an initial count. A value from the group as well as a predetermined value are p... | 08/07/2001 |
| 6172629 | Multistage analog-to-digital converter employing dither There is disclosed, a converter for converting an input signal from one form to another. The converter includes a slicing circuit adapted to slice a signal into levels. The slicing circuit includes at least one threshold for establishing slicing levels. D... | 01/09/2001 |
| 6173161 | Signal improvement by predistortion/postdistortion programmable converter In accordance with the present invention, a communications system transmits a predetermined signal, from a first, sending, end of a communications system to a second, receiving, end of a communications system. The predetermined signal is distorted by the ... | 01/09/2001 |
| 6163563 | Digital communication system for high-speed complex correlation A receiver for a spread spectrum communication system is disclosed in which a transmitter transmits a data signal to a receiver includes a memory for storing digital representation of the data signal received by the receiver. A memory input addressing uni... | 12/19/2000 |
| 6157338 | Deterministic successive approximation analog-to-digital converter An integrated circuit which includes a successive approximation analog-to-digital converter. The successive approximation analog-to-digital converter employs oppositely coupled comparators and logic circuitry to generate a signal upon a bit determination,... | 12/05/2000 |
| 6154164 | Variable clock rate analog-to-digital converter There is disclosed an integrated circuit including a successive approximation analog-to-digital converter. The successive approximation analog-to-digital converter can select which of at least two clock signals of different frequency drive the successive ... | 11/28/2000 |
| 6154165 | Variable clock rate, variable bit-depth analog-to-digital converter An integrated circuit includes a variable bit-depth successive approximation analog-to-digital converter. The variable bit-depth successive approximation analog-to-digital converter can select from at least two clock signals of different frequencies to dr... | 11/28/2000 |
| 6150885 | Transconductance amplifier with wideband noise filtering There is disclosed a transconductance amplifier receives a voltage input and provides a current output. The transconductance amplifier includes a current mirror having a lowpass filter between transistors implementing the current mirror.... | 11/21/2000 |
| 6122655 | Efficient use of inverting cells in multiplier converter A multiplier generates an array of partial products. The partial products are reduced in a converter having cells defining rows and columns. Cells adjacent to adders alternate between a cell that provides non-inverted outputs and a cell that provides inve... | 09/19/2000 |
| 6107949 | Flash analog-to-digital converter with matrix-switched comparators An integrated circuit includes a converter for converting a signal from one form to another, one of the forms being analog and the other form being digital. The converter includes a voltage gradient having a plurality of MSB taps spaced there-along with t... | 08/22/2000 |
| 6073228 | Modulo address generator for generating an updated address A modulo address generation circuit for generating multiple-word memory accesses for use in a computer system. The circuit includes an address pointer latch for retaining a current address pointer, an adder for receiving the current address pointer as a f... | 06/06/2000 |
| 6064712 | Autoreload loop counter There is disclosed a loop counter reload circuit loads an initial count value into a counter and a shadow register. A count value output from the counter is changed by a predetermined displacement resulting in a changed count value. The count value from t... | 05/16/2000 |
| 6051989 | Active termination of a conductor for bi-directional signal transmission There is disclosed, an active termination circuit includes a transmitter adapted to be coupled to a bidirectional conductor, a receiver also adapted to be coupled to the bidirectional conductor, a first impedance adapted to be switched to couple to the bi... | 04/18/2000 |
| 6049858 | Modulo address generator with precomputed comparison and correction terms In accordance with the present invention, an address arithmetic unit provides a modulo addressing technique for addressing memory locations in a circular buffer. The address arithmetic unit includes a sign detector adapted to determine whether a sum of an... | 04/11/2000 |
| 6047364 | True modulo addressing generator In accordance with the present invention, an address arithmetic unit provides a modulo addressing technique for addressing a circular buffer. The address arithmetic unit includes a first selector adapted to receive as a first input a value representative ... | 04/04/2000 |
| 6037006 | Method and fixture for laser bar facet coating A method and fixture for laser bar facet coating are disclosed. A holder for securing devices having surfaces for coating includes first and second channels. A plurality of web slats are received in the channels. The web slats have first and second ends a... | 03/14/2000 |
| 6034631 | Comparator error correction in flash analog-to-digital converter There is disclosed, a converter for converting an input signal from one form to another includes a generator circuit for generating as a thermometer code a plurality of binary signals from the input signal. The converter includes one or more enhanced majo... | 03/07/2000 |
| 6031887 | High-speed binary synchronous counter An integrated circuit includes an n-bit counter having a plurality of k subcounters where both n and k are integers. At least one of the subcounters includes a switchable device adapted to receive a carry-out signal from an adjacent subcounter as a first ... | 02/29/2000 |
| 6028466 | Integrated circuit including high transconductance voltage clamp An IC includes a clamp transistor for limiting the voltage at a circuit node and a current amplifier coupled across the input and output terminals of the clamp transistor. In one embodiment the current amplifier comprises a current mirror. In a differenti... | 02/22/2000 |
| 6029267 | Single-cycle, soft decision, compare-select operation using dual-add processor In accordance with the invention, a method of generating a soft symbol confidence level for use in decoding a received digital signal includes calculating a difference between two potential next state accumulated costs to provide a soft symbol confidence ... | 02/22/2000 |
| 6018758 | Squarer with diagonal row merged into folded partial product array A squarer generates an array of partial products. A method of squaring a representation of a number includes generating an array of partial products, combining the partial product on one side of a diagonal of the array with partial products on the other s... | 01/25/2000 |
| 6009128 | Metric acceleration on dual MAC processor There is disclosed, a method and apparatus for processing a signal in a pipeline. The method includes retrieving a present state cost. Simultaneously with receiving the present state cost, an estimated symbol and a received symbol are obtained, a differen... | 12/28/1999 |
| 5983333 | High speed module address generator In accordance with the present invention, an address arithmetic unit provides a modulo addressing technique for addressing memory locations in a circular buffer. The address arithmetic unit includes a first selector adapted to receive as a first input a v... | 11/09/1999 |
| 5977864 | High speed comparator with bit-wise masking There is disclosed, a high speed comparator with bit-wise masking takes advantage of early availability of the reference word and mask word to generate conditional select signals, thereby minimizing the time required to generate a comparator output once t... | 11/02/1999 |
| 5978826 | Adder with even/odd 1-bit adder cells An integrated circuit including an adder that is a series of one-bit cascaded adder cells. The circuits that implement the adder cells are not all alike. The adder cells are of two types: an even adder cell and an odd adder cell. The even adder cells rece... | 11/02/1999 |
| 5959564 | Broken thermometer code and comparator error correction by pseudo majority gate decoding in analog-to-digital converters There is disclosed, a converter for converting an input signal from one form to another includes a generator circuit for generating as a thermometer code a plurality of binary signals from the input signal. The converter includes one or more pseudo-majori... | 09/28/1999 |
| 5948050 | Fast conversion two's complement encoded shift value for a barrel shifter In accordance with the present invention, a method and apparatus are provided for controlling an N-bit barrel shifter to shift the bits of an input word by a shift value. The method includes the steps of performing a ones' complement of an m-bit binary re... | 09/07/1999 |
| 5928317 | Fast converter for left-to-right carry-free multiplier A multiplier generates an array of partial products. The partial products are reduced in the more significant side of the array assuming a carry-out from the less significant side of the array as taking on a first state to produce a first set of reduced p... | 07/27/1999 |
| 5929666 | Bootstrap circuit Briefly, in accordance with one embodiment of the invention, a bootstrap circuit comprises a pair of drivers coupled together so as to form a bootstrap node and a bipolar transistor coupled to the bootstrap node. A method of using a bipolar transistor in ... | 07/27/1999 |
